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Merge pull request #14197 from benpicco/driver/at86rf215_cleanup

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driver/at86rf215: cleanup
This commit is contained in:
Leandro Lanzieri 2020-06-09 18:38:57 +02:00 committed by GitHub
commit ab996823ee
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 168 additions and 25 deletions
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94
drivers/at86rf215/Kconfig
View File

@ -38,4 +38,98 @@ config AT86RF215_TRIM_VAL
26 MHz the best. 26 MHz the best.
For more information Refer Table 6-25 TRIM in Datasheet For more information Refer Table 6-25 TRIM in Datasheet
choice
prompt "Default Modulation"
config AT86RF215_DEFAULT_LEGACY_OQPSK
bool "legacy O-QPSK"
help
O-QPSK compatible with IEEE 802.15.4-2003 devices
config AT86RF215_DEFAULT_MR_OQPSK
bool "MR-O-QPSK"
help
MR-O-QPSK according to IEEE 802.15.4g
config AT86RF215_DEFAULT_MR_OFDM
bool "MR-OFDM"
help
MR-O-OFDM according to IEEE 802.15.4g
endchoice
menu "O-QPSK (802.15.4) configuration"
depends on AT86RF215_DEFAULT_LEGACY_OQPSK
config AT86RF215_DEFAULT_OQPSK_RATE
int "Default (legacy) O-QPSK rate mode"
range 0 1
default 0
help
The at86rf215 supports proprietary high data rates that are compatible
with the at86rf2xx parts.
Set this to 1 to configure the proprietary high-data rate option as default.
If unsure, leave this at 0.
endmenu # legacy O-QPSK
menu "MR-O-QPSK (802.15.4g) configuration"
depends on AT86RF215_DEFAULT_MR_OQPSK
config AT86RF215_DEFAULT_MR_OQPSK_RATE
int "Default MR-O-QPSK rate mode"
range 0 3
default 2
help
Default Rate Mode of the MR-O-QPSK PHY
Each increment doubles the PSDU data rate.
choice
prompt "Default MR-O-QPSK Chip Rate"
config AT86RF215_DEFAULT_MR_OQPSK_CHIPS_100
bool "100 kchip/s"
config AT86RF215_DEFAULT_MR_OQPSK_CHIPS_200
bool "200 kchip/s"
config AT86RF215_DEFAULT_MR_OQPSK_CHIPS_1000
bool "1000 kchip/s"
config AT86RF215_DEFAULT_MR_OQPSK_CHIPS_2000
bool "2000 kchip/s"
endchoice
endmenu # MR-O-QPSK
menu "MR-OFDM (802.15.4g) configuration"
depends on AT86RF215_DEFAULT_MR_OFDM
config AT86RF215_DEFAULT_MR_OFDM_OPT
int "Default MR-OFDM option"
range 1 4
default 2
help
Default Option of the MR-OFDM PHY
Each increment halves the PSDU data rate.
config AT86RF215_DEFAULT_MR_OFDM_MCS
int "Default MR-OFDM Modulation & Coding Scheme"
range 0 6
default 2
help
Default Modulation & Coding Scheme of the MR-OFDM PHY.
Higher schemes correspond to higher data rates and lower range.
0: BPSK, rate 1⁄2, 4 x frequency repetition
1: BPSK, rate 1⁄2, 2 x frequency repetition
2: QPSK, rate 1⁄2, 2 x frequency repetition
3: QPSK, rate 1⁄2
4: QPSK, rate 3⁄4
5: 16-QAM, rate 1⁄2
6: 16-QAM, rate 3⁄4
endmenu
endif # KCONFIG_MODULE_AT86RF215 endif # KCONFIG_MODULE_AT86RF215

19
drivers/at86rf215/at86rf215.c
View File

@ -18,6 +18,7 @@
*/ */
#include "luid.h" #include "luid.h"
#include "board.h"
#include "byteorder.h" #include "byteorder.h"
#include "net/ieee802154.h" #include "net/ieee802154.h"
#include "net/gnrc.h" #include "net/gnrc.h"
@ -66,9 +67,9 @@ void at86rf215_reset_and_cfg(at86rf215_t *dev)
luid_get_eui64((eui64_t *)&dev->netdev.long_addr); luid_get_eui64((eui64_t *)&dev->netdev.long_addr);
if (is_subGHz(dev)) { if (is_subGHz(dev)) {
dev->netdev.chan = AT86RF215_DEFAULT_SUBGHZ_CHANNEL; dev->netdev.chan = CONFIG_AT86RF215_DEFAULT_SUBGHZ_CHANNEL;
} else { } else {
dev->netdev.chan = AT86RF215_DEFAULT_CHANNEL; dev->netdev.chan = CONFIG_AT86RF215_DEFAULT_CHANNEL;
} }
dev->netdev.pan = CONFIG_IEEE802154_DEFAULT_PANID; dev->netdev.pan = CONFIG_IEEE802154_DEFAULT_PANID;
@ -144,14 +145,14 @@ if (!IS_ACTIVE(CONFIG_AT86RF215_USE_CLOCK_OUTPUT)){
at86rf215_reg_write(dev, dev->BBC->RG_AMCS, reg); at86rf215_reg_write(dev, dev->BBC->RG_AMCS, reg);
if (AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_OQPSK) { if (CONFIG_AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_OQPSK) {
at86rf215_configure_legacy_OQPSK(dev, 0); at86rf215_configure_legacy_OQPSK(dev, CONFIG_AT86RF215_DEFAULT_OQPSK_RATE);
} }
if (AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_MR_OQPSK) { if (CONFIG_AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_MR_OQPSK) {
at86rf215_configure_OQPSK(dev, AT86RF215_DEFAULT_MR_OQPSK_CHIPS, at86rf215_configure_OQPSK(dev, CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS,
AT86RF215_DEFAULT_MR_OQPSK_RATE); CONFIG_AT86RF215_DEFAULT_MR_OQPSK_RATE);
} }
if (AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_MR_OFDM) { if (CONFIG_AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_MR_OFDM) {
at86rf215_configure_OFDM(dev, CONFIG_AT86RF215_DEFAULT_MR_OFDM_OPT, at86rf215_configure_OFDM(dev, CONFIG_AT86RF215_DEFAULT_MR_OFDM_OPT,
CONFIG_AT86RF215_DEFAULT_MR_OFDM_MCS); CONFIG_AT86RF215_DEFAULT_MR_OFDM_MCS);
} }
@ -169,7 +170,7 @@ if (!IS_ACTIVE(CONFIG_AT86RF215_USE_CLOCK_OUTPUT)){
at86rf215_set_pan(dev, 0, dev->netdev.pan); at86rf215_set_pan(dev, 0, dev->netdev.pan);
/* set default TX power */ /* set default TX power */
at86rf215_set_txpower(dev, AT86RF215_DEFAULT_TXPOWER); at86rf215_set_txpower(dev, CONFIG_AT86RF215_DEFAULT_TXPOWER);
/* start listening for incoming packets */ /* start listening for incoming packets */
at86rf215_rf_cmd(dev, CMD_RF_RX); at86rf215_rf_cmd(dev, CMD_RF_RX);

24
drivers/at86rf215/at86rf215_netdev.c
View File

@ -394,6 +394,7 @@ static int _get(netdev_t *netdev, netopt_t opt, void *val, size_t max_len)
res = max_len; res = max_len;
break; break;
#ifdef MODULE_NETDEV_IEEE802154_MR_OFDM
case NETOPT_MR_OFDM_OPTION: case NETOPT_MR_OFDM_OPTION:
assert(max_len >= sizeof(int8_t)); assert(max_len >= sizeof(int8_t));
*((int8_t *)val) = at86rf215_OFDM_get_option(dev); *((int8_t *)val) = at86rf215_OFDM_get_option(dev);
@ -405,7 +406,8 @@ static int _get(netdev_t *netdev, netopt_t opt, void *val, size_t max_len)
*((int8_t *)val) = at86rf215_OFDM_get_scheme(dev); *((int8_t *)val) = at86rf215_OFDM_get_scheme(dev);
res = max_len; res = max_len;
break; break;
#endif /* MODULE_NETDEV_IEEE802154_MR_OFDM */
#ifdef MODULE_NETDEV_IEEE802154_MR_OQPSK
case NETOPT_MR_OQPSK_CHIPS: case NETOPT_MR_OQPSK_CHIPS:
assert(max_len >= sizeof(int16_t)); assert(max_len >= sizeof(int16_t));
switch (at86rf215_OQPSK_get_chips(dev)) { switch (at86rf215_OQPSK_get_chips(dev)) {
@ -422,13 +424,14 @@ static int _get(netdev_t *netdev, netopt_t opt, void *val, size_t max_len)
*((int8_t *)val) = at86rf215_OQPSK_get_mode(dev); *((int8_t *)val) = at86rf215_OQPSK_get_mode(dev);
res = max_len; res = max_len;
break; break;
#endif /* MODULE_NETDEV_IEEE802154_MR_OQPSK */
#ifdef MODULE_NETDEV_IEEE802154_OQPSK
case NETOPT_OQPSK_RATE: case NETOPT_OQPSK_RATE:
assert(max_len >= sizeof(int8_t)); assert(max_len >= sizeof(int8_t));
*((int8_t *)val) = at86rf215_OQPSK_get_mode_legacy(dev); *((int8_t *)val) = at86rf215_OQPSK_get_mode_legacy(dev);
res = max_len; res = max_len;
break; break;
#endif /* MODULE_NETDEV_IEEE802154_OQPSK */
default: default:
res = -ENOTSUP; res = -ENOTSUP;
break; break;
@ -576,27 +579,34 @@ static int _set(netdev_t *netdev, netopt_t opt, const void *val, size_t len)
case NETOPT_IEEE802154_PHY: case NETOPT_IEEE802154_PHY:
assert(len <= sizeof(uint8_t)); assert(len <= sizeof(uint8_t));
switch (*(uint8_t *)val) { switch (*(uint8_t *)val) {
#ifdef MODULE_NETDEV_IEEE802154_OQPSK
case IEEE802154_PHY_OQPSK: case IEEE802154_PHY_OQPSK:
at86rf215_configure_legacy_OQPSK(dev, at86rf215_OQPSK_get_mode_legacy(dev)); at86rf215_configure_legacy_OQPSK(dev, at86rf215_OQPSK_get_mode_legacy(dev));
res = sizeof(uint8_t); res = sizeof(uint8_t);
break; break;
#endif /* MODULE_NETDEV_IEEE802154_OQPSK */
#ifdef MODULE_NETDEV_IEEE802154_MR_OQPSK
case IEEE802154_PHY_MR_OQPSK: case IEEE802154_PHY_MR_OQPSK:
at86rf215_configure_OQPSK(dev, at86rf215_configure_OQPSK(dev,
at86rf215_OQPSK_get_chips(dev), at86rf215_OQPSK_get_chips(dev),
at86rf215_OQPSK_get_mode(dev)); at86rf215_OQPSK_get_mode(dev));
res = sizeof(uint8_t); res = sizeof(uint8_t);
break; break;
#endif /* MODULE_NETDEV_IEEE802154_MR_OQPSK */
#ifdef MODULE_NETDEV_IEEE802154_MR_OFDM
case IEEE802154_PHY_MR_OFDM: case IEEE802154_PHY_MR_OFDM:
at86rf215_configure_OFDM(dev, at86rf215_configure_OFDM(dev,
at86rf215_OFDM_get_option(dev), at86rf215_OFDM_get_option(dev),
at86rf215_OFDM_get_scheme(dev)); at86rf215_OFDM_get_scheme(dev));
res = sizeof(uint8_t); res = sizeof(uint8_t);
break; break;
#endif /* MODULE_NETDEV_IEEE802154_MR_OFDM */
default: default:
return -ENOTSUP; return -ENOTSUP;
} }
break; break;
#ifdef MODULE_NETDEV_IEEE802154_MR_OFDM
case NETOPT_MR_OFDM_OPTION: case NETOPT_MR_OFDM_OPTION:
if (at86rf215_get_phy_mode(dev) != IEEE802154_PHY_MR_OFDM) { if (at86rf215_get_phy_mode(dev) != IEEE802154_PHY_MR_OFDM) {
return -ENOTSUP; return -ENOTSUP;
@ -622,7 +632,8 @@ static int _set(netdev_t *netdev, netopt_t opt, const void *val, size_t len)
res = -ERANGE; res = -ERANGE;
} }
break; break;
#endif /* MODULE_NETDEV_IEEE802154_MR_OFDM */
#ifdef MODULE_NETDEV_IEEE802154_MR_OQPSK
case NETOPT_MR_OQPSK_CHIPS: case NETOPT_MR_OQPSK_CHIPS:
if (at86rf215_get_phy_mode(dev) != IEEE802154_PHY_MR_OQPSK) { if (at86rf215_get_phy_mode(dev) != IEEE802154_PHY_MR_OQPSK) {
return -ENOTSUP; return -ENOTSUP;
@ -662,7 +673,8 @@ static int _set(netdev_t *netdev, netopt_t opt, const void *val, size_t len)
res = -ERANGE; res = -ERANGE;
} }
break; break;
#endif /* MODULE_NETDEV_IEEE802154_MR_OQPSK */
#ifdef MODULE_NETDEV_IEEE802154_OQPSK
case NETOPT_OQPSK_RATE: case NETOPT_OQPSK_RATE:
if (at86rf215_get_phy_mode(dev) != IEEE802154_PHY_OQPSK) { if (at86rf215_get_phy_mode(dev) != IEEE802154_PHY_OQPSK) {
return -ENOTSUP; return -ENOTSUP;
@ -675,7 +687,7 @@ static int _set(netdev_t *netdev, netopt_t opt, const void *val, size_t len)
res = -ERANGE; res = -ERANGE;
} }
break; break;
#endif /* MODULE_NETDEV_IEEE802154_OQPSK */
default: default:
break; break;
} }

56
drivers/include/at86rf215.h
View File

@ -100,22 +100,44 @@ enum {
*/ */
#define CONFIG_AT86RF215_TRIM_VAL (0) #define CONFIG_AT86RF215_TRIM_VAL (0)
#endif #endif
/** @} */
/** /**
* @name Channel configuration * @name Channel configuration
* @{ * @{
*/ */
#define AT86RF215_DEFAULT_CHANNEL (CONFIG_IEEE802154_DEFAULT_CHANNEL) #ifndef CONFIG_AT86RF215_DEFAULT_CHANNEL
#define AT86RF215_DEFAULT_SUBGHZ_CHANNEL (CONFIG_IEEE802154_DEFAULT_SUBGHZ_CHANNEL) #define CONFIG_AT86RF215_DEFAULT_CHANNEL (CONFIG_IEEE802154_DEFAULT_CHANNEL)
#endif
#ifndef CONFIG_AT86RF215_DEFAULT_SUBGHZ_CHANNEL
#define CONFIG_AT86RF215_DEFAULT_SUBGHZ_CHANNEL (CONFIG_IEEE802154_DEFAULT_SUBGHZ_CHANNEL)
#endif
/** @} */ /** @} */
/** /**
* @name Default PHY Mode * @name Default PHY Mode
* @{ * @{
*/ */
#ifndef AT86RF215_DEFAULT_PHY_MODE #if IS_ACTIVE(CONFIG_AT86RF215_DEFAULT_LEGACY_OQPSK)
#define AT86RF215_DEFAULT_PHY_MODE (IEEE802154_PHY_OQPSK) #define CONFIG_AT86RF215_DEFAULT_PHY_MODE (IEEE802154_PHY_OQPSK)
#elif IS_ACTIVE(CONFIG_AT86RF215_DEFAULT_MR_OQPSK)
#define CONFIG_AT86RF215_DEFAULT_PHY_MODE (IEEE802154_PHY_MR_OQPSK)
#elif IS_ACTIVE(CONFIG_AT86RF215_DEFAULT_MR_OFDM)
#define CONFIG_AT86RF215_DEFAULT_PHY_MODE (IEEE802154_PHY_MR_OFDM)
#endif
#ifndef CONFIG_AT86RF215_DEFAULT_PHY_MODE
#define CONFIG_AT86RF215_DEFAULT_PHY_MODE (IEEE802154_PHY_OQPSK)
#endif
/** @} */
/**
* @name Default O-QPSK Rate Mode
* Non-zero value enables proprietary high data rate by default
* @{
*/
#ifndef CONFIG_AT86RF215_DEFAULT_OQPSK_RATE
#define CONFIG_AT86RF215_DEFAULT_OQPSK_RATE (0)
#endif #endif
/** @} */ /** @} */
@ -123,8 +145,18 @@ enum {
* @name Default MR-O-QPSK Chip Rate * @name Default MR-O-QPSK Chip Rate
* @{ * @{
*/ */
#ifndef AT86RF215_DEFAULT_MR_OQPSK_CHIPS #if IS_ACTIVE(CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS_100)
#define AT86RF215_DEFAULT_MR_OQPSK_CHIPS (AT86RF215_FCHIP_1000) #define CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS (AT86RF215_FCHIP_100)
#elif IS_ACTIVE(CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS_200)
#define CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS (AT86RF215_FCHIP_200)
#elif IS_ACTIVE(CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS_1000)
#define CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS (AT86RF215_FCHIP_1000)
#elif IS_ACTIVE(CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS_2000)
#define CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS (AT86RF215_FCHIP_2000)
#endif
#ifndef CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS
#define CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS (AT86RF215_FCHIP_1000)
#endif #endif
/** @} */ /** @} */
@ -132,8 +164,8 @@ enum {
* @name Default MR-O-QPSK Rate Mode * @name Default MR-O-QPSK Rate Mode
* @{ * @{
*/ */
#ifndef AT86RF215_DEFAULT_MR_OQPSK_RATE #ifndef CONFIG_AT86RF215_DEFAULT_MR_OQPSK_RATE
#define AT86RF215_DEFAULT_MR_OQPSK_RATE (2) #define CONFIG_AT86RF215_DEFAULT_MR_OQPSK_RATE (2)
#endif #endif
/** @} */ /** @} */
@ -158,7 +190,11 @@ enum {
/** /**
* @brief Default TX power (0dBm) * @brief Default TX power (0dBm)
*/ */
#define AT86RF215_DEFAULT_TXPOWER (CONFIG_IEEE802154_DEFAULT_TXPOWER) #ifndef CONFIG_AT86RF215_DEFAULT_TXPOWER
#define CONFIG_AT86RF215_DEFAULT_TXPOWER (CONFIG_IEEE802154_DEFAULT_TXPOWER)
#endif
/** @} */
/** /**
* @name Flags for device internal states (see datasheet) * @name Flags for device internal states (see datasheet)