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Merge pull request #14069 from benpicco/cpu/nrf52-cleanup

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cpu/nrf52: update & fix vendor files, derive flash settings
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Koen Zandberg 2020-05-19 10:55:50 +02:00 committed by GitHub
commit b15c4ef418
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6 changed files with 1876 additions and 1386 deletions
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10
cpu/nrf52/include/cpu_conf.h
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@ -66,13 +66,11 @@ extern "C" {
* @brief Flash page configuration * @brief Flash page configuration
* @{ * @{
*/ */
#define FLASHPAGE_SIZE (4096U) #ifdef BPROT_PRESENT
#define FLASHPAGE_SIZE BPROT_REGIONS_SIZE
#if defined(CPU_MODEL_NRF52811XXAA) #define FLASHPAGE_NUMOF BPROT_REGIONS_NUM
#define FLASHPAGE_NUMOF (48U)
#elif defined(CPU_MODEL_NRF52832XXAA)
#define FLASHPAGE_NUMOF (128U)
#elif defined(CPU_MODEL_NRF52840XXAA) #elif defined(CPU_MODEL_NRF52840XXAA)
#define FLASHPAGE_SIZE (4096U)
#define FLASHPAGE_NUMOF (256U) #define FLASHPAGE_NUMOF (256U)
#endif #endif

16
cpu/nrf52/include/vendor/nrf52.h vendored
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
@ -30,10 +30,10 @@
* @file nrf52.h * @file nrf52.h
* @brief CMSIS HeaderFile * @brief CMSIS HeaderFile
* @version 1 * @version 1
* @date 06. June 2018 * @date 04. March 2020
* @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:38 * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:52
* from File 'nrf52.svd', * from File 'nrf52.svd',
* last modified on Wednesday, 06.06.2018 13:21:34 * last modified on Wednesday, 04.03.2020 13:56:43
*/ */
@ -128,10 +128,12 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */
#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1 /*!< MPU present or not */ #define __MPU_PRESENT 1 /*!< MPU present */
#define __FPU_PRESENT 1 /*!< FPU present or not */ #define __FPU_PRESENT 1 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */ /** @} */ /* End of group Configuration_of_CMSIS */
@ -2415,7 +2417,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
#pragma pop #pragma pop
#elif defined (__ICCARM__) #elif defined (__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop #pragma clang diagnostic pop
#elif defined (__GNUC__) #elif defined (__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */

1
cpu/nrf52/include/vendor/nrf52811.h vendored
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@ -129,7 +129,6 @@ typedef enum {
/** @} */ /* End of group Configuration_of_CMSIS */ /** @} */ /* End of group Configuration_of_CMSIS */
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
#include "system_nrf52811.h" /*!< nrf52811 System */
#ifndef __IM /*!< Fallback for older CMSIS versions */ #ifndef __IM /*!< Fallback for older CMSIS versions */
#define __IM __I #define __IM __I

451
cpu/nrf52/include/vendor/nrf52840.h vendored
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
@ -30,10 +30,10 @@
* @file nrf52840.h * @file nrf52840.h
* @brief CMSIS HeaderFile * @brief CMSIS HeaderFile
* @version 1 * @version 1
* @date 06. June 2018 * @date 04. March 2020
* @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:39 * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:52
* from File 'nrf52840.svd', * from File 'nrf52840.svd',
* last modified on Wednesday, 06.06.2018 13:21:35 * last modified on Wednesday, 04.03.2020 13:56:44
*/ */
@ -134,10 +134,12 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ #define __CM4_REV 0x0001U /*!< CM4 Core Revision */
#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1 /*!< MPU present or not */ #define __MPU_PRESENT 1 /*!< MPU present */
#define __FPU_PRESENT 1 /*!< FPU present or not */ #define __FPU_PRESENT 1 /*!< FPU present */
/** @} */ /* End of group Configuration_of_CMSIS */ /** @} */ /* End of group Configuration_of_CMSIS */
@ -199,8 +201,7 @@ typedef struct {
__IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */
__IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */
__IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */
__IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ } FICR_INFO_Type; /*!< Size = 20 (0x14) */
} FICR_INFO_Type; /*!< Size = 32 (0x20) */
/** /**
@ -233,16 +234,16 @@ typedef struct {
typedef struct { typedef struct {
__IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read
these values to populate NFCID1_3RD_LAST, these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST. */ NFCID1_2ND_LAST, and NFCID1_LAST. */
__IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read
these values to populate NFCID1_3RD_LAST, these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST. */ NFCID1_2ND_LAST, and NFCID1_LAST. */
__IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read
these values to populate NFCID1_3RD_LAST, these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST. */ NFCID1_2ND_LAST, and NFCID1_LAST. */
__IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read
these values to populate NFCID1_3RD_LAST, these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST. */ NFCID1_2ND_LAST, and NFCID1_LAST. */
} FICR_NFC_Type; /*!< Size = 16 (0x10) */ } FICR_NFC_Type; /*!< Size = 16 (0x10) */
@ -265,10 +266,9 @@ typedef struct {
* @brief POWER_RAM [RAM] (Unspecified) * @brief POWER_RAM [RAM] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register */ __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */
__OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */
register */ __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear
__OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear
register */ register */
__IM uint32_t RESERVED; __IM uint32_t RESERVED;
} POWER_RAM_Type; /*!< Size = 16 (0x10) */ } POWER_RAM_Type; /*!< Size = 16 (0x10) */
@ -388,7 +388,8 @@ typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */
} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
} SPIS_RXD_Type; /*!< Size = 16 (0x10) */
/** /**
@ -398,7 +399,8 @@ typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */
} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
} SPIS_TXD_Type; /*!< Size = 16 (0x10) */
/** /**
@ -457,7 +459,8 @@ typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */
} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
} TWIS_RXD_Type; /*!< Size = 16 (0x10) */
/** /**
@ -467,7 +470,8 @@ typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */
} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
} TWIS_TXD_Type; /*!< Size = 16 (0x10) */
/** /**
@ -497,13 +501,13 @@ typedef struct {
/** /**
* @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.)
*/ */
typedef struct { typedef struct {
__IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last result is equal __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or
or above CH[n].LIMIT.HIGH */ above CH[n].LIMIT.HIGH */
__IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last result is equal __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or
or below CH[n].LIMIT.LOW */ below CH[n].LIMIT.LOW */
} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */
@ -511,13 +515,13 @@ typedef struct {
* @brief SAADC_CH [CH] (Unspecified) * @brief SAADC_CH [CH] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection
for CH[n] */ for CH[n] */
__IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection
for CH[n] */ for CH[n] */
__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for
CH[n] */ CH[n] */
__IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event
monitoring of a channel */ monitoring of a channel */
} SAADC_CH_Type; /*!< Size = 16 (0x10) */ } SAADC_CH_Type; /*!< Size = 16 (0x10) */
@ -548,15 +552,14 @@ typedef struct {
* @brief PWM_SEQ [SEQ] (Unspecified) * @brief PWM_SEQ [SEQ] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM
RAM of this sequence */ of this sequence */
__IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles)
cycles) in this sequence */ in this sequence */
__IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM
PWM periods between samples loaded into periods between samples loaded into compare
compare register */ register */
__IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */
sequence */
__IM uint32_t RESERVED[4]; __IM uint32_t RESERVED[4];
} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ } PWM_SEQ_Type; /*!< Size = 32 (0x20) */
@ -565,8 +568,8 @@ typedef struct {
* @brief PWM_PSEL [PSEL] (Unspecified) * @brief PWM_PSEL [PSEL] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for
for PWM channel n */ PWM channel n */
} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ } PWM_PSEL_Type; /*!< Size = 16 (0x10) */
@ -594,15 +597,15 @@ typedef struct {
* @brief ACL_ACL [ACL] (Unspecified) * @brief ACL_ACL [ACL] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster[n]: Configure the word-aligned __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned
start address of region n to protect */ start address of region n to protect */
__IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster[n]: Size of region to protect __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect
counting from address ACL[n].ADDR. Write counting from address ACL[n].ADDR. Write
'0' as no effect. */ '0' as no effect. */
__IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster[n]: Access permissions for __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region
region n as defined by start address ACL[n].ADDR n as defined by start address ACL[n].ADDR
and size ACL[n].SIZE */ and size ACL[n].SIZE */
__IOM uint32_t UNUSED0; /*!< (@ 0x0000000C) Unspecified */ __IM uint32_t RESERVED;
} ACL_ACL_Type; /*!< Size = 16 (0x10) */ } ACL_ACL_Type; /*!< Size = 16 (0x10) */
@ -610,10 +613,8 @@ typedef struct {
* @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks)
*/ */
typedef struct { typedef struct {
__OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */
n */ __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */
__OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group
n */
} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */
@ -621,8 +622,8 @@ typedef struct {
* @brief PPI_CH [CH] (PPI Channel) * @brief PPI_CH [CH] (PPI Channel)
*/ */
typedef struct { typedef struct {
__IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */
__IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */
} PPI_CH_Type; /*!< Size = 8 (0x8) */ } PPI_CH_Type; /*!< Size = 8 (0x8) */
@ -630,28 +631,28 @@ typedef struct {
* @brief PPI_FORK [FORK] (Fork) * @brief PPI_FORK [FORK] (Fork)
*/ */
typedef struct { typedef struct {
__IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */
} PPI_FORK_Type; /*!< Size = 4 (0x4) */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */
/** /**
* @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.)
*/ */
typedef struct { typedef struct {
__IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to region __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n
n detected */ detected */
__IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to region __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n
n detected */ detected */
} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */
/** /**
* @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.)
*/ */
typedef struct { typedef struct {
__IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to peripheral __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral
region n detected */ region n detected */
__IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to peripheral __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral
region n detected */ region n detected */
} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */
@ -660,11 +661,11 @@ typedef struct {
* @brief MWU_PERREGION [PERREGION] (Unspecified) * @brief MWU_PERREGION [PERREGION] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[n]: Source of event/interrupt __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt
in region n, write access detected while in region n, write access detected while
corresponding subregion was enabled for corresponding subregion was enabled for
watching */ watching */
__IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[n]: Source of event/interrupt __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt
in region n, read access detected while in region n, read access detected while
corresponding subregion was enabled for corresponding subregion was enabled for
watching */ watching */
@ -675,10 +676,9 @@ typedef struct {
* @brief MWU_REGION [REGION] (Unspecified) * @brief MWU_REGION [REGION] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Start address for region __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region
n */
__IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: End address of region
n */ n */
__IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */
__IM uint32_t RESERVED[2]; __IM uint32_t RESERVED[2];
} MWU_REGION_Type; /*!< Size = 16 (0x10) */ } MWU_REGION_Type; /*!< Size = 16 (0x10) */
@ -687,10 +687,9 @@ typedef struct {
* @brief MWU_PREGION [PREGION] (Unspecified) * @brief MWU_PREGION [PREGION] (Unspecified)
*/ */
typedef struct { typedef struct {
__IM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Reserved for future use */ __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */
__IM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: Reserved for future use */ __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */
__IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[n]: Subregions of region __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */
n */
__IM uint32_t RESERVED; __IM uint32_t RESERVED;
} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ } MWU_PREGION_Type; /*!< Size = 16 (0x10) */
@ -752,13 +751,13 @@ typedef struct {
* @brief USBD_HALTED [HALTED] (Unspecified) * @brief USBD_HALTED [HALTED] (Unspecified)
*/ */
typedef struct { typedef struct {
__IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection[n]: IN endpoint halted __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status.
status. Can be used as is as response to Can be used as is as response to a GetStatus()
a GetStatus() request to endpoint. */ request to endpoint. */
__IM uint32_t RESERVED; __IM uint32_t RESERVED;
__IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection[n]: OUT endpoint halted __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status.
status. Can be used as is as response to Can be used as is as response to a GetStatus()
a GetStatus() request to endpoint. */ request to endpoint. */
} USBD_HALTED_Type; /*!< Size = 68 (0x44) */ } USBD_HALTED_Type; /*!< Size = 68 (0x44) */
@ -766,7 +765,7 @@ typedef struct {
* @brief USBD_SIZE [SIZE] (Unspecified) * @brief USBD_SIZE [SIZE] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection[n]: Number of bytes received __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received
last in the data stage of this OUT endpoint */ last in the data stage of this OUT endpoint */
__IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT
data endpoint */ data endpoint */
@ -777,10 +776,10 @@ typedef struct {
* @brief USBD_EPIN [EPIN] (Unspecified) * @brief USBD_EPIN [EPIN] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes
to transfer */ to transfer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred
in the last transaction */ in the last transaction */
__IM uint32_t RESERVED[2]; __IM uint32_t RESERVED[2];
} USBD_EPIN_Type; /*!< Size = 20 (0x14) */ } USBD_EPIN_Type; /*!< Size = 20 (0x14) */
@ -800,10 +799,10 @@ typedef struct {
* @brief USBD_EPOUT [EPOUT] (Unspecified) * @brief USBD_EPOUT [EPOUT] (Unspecified)
*/ */
typedef struct { typedef struct {
__IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */
__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes
to transfer */ to transfer */
__IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred
in the last transaction */ in the last transaction */
__IM uint32_t RESERVED[2]; __IM uint32_t RESERVED[2];
} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */
@ -890,21 +889,20 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu
__IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */
__IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */
__IM uint32_t RESERVED1[18]; __IM uint32_t RESERVED1[18];
__IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */
__IM uint32_t RESERVED2[6]; __IM uint32_t RESERVED2[6];
__IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word
n */
__IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity Root, word
n */ n */
__IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */
__IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */
__IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */
__IM uint32_t RESERVED3[21]; __IM uint32_t RESERVED3[21];
__IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */
__IM uint32_t RESERVED4[140]; __IM uint32_t RESERVED4[143];
__IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection[n]: Production test signature __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature
n */ n */
__IM uint32_t RESERVED5[42]; __IM uint32_t RESERVED5[42];
__IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization
coefficients */ coefficients */
__IM uint32_t RESERVED6[2]; __IM uint32_t RESERVED6[2];
__IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */
@ -924,26 +922,24 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu
*/ */
typedef struct { /*!< (@ 0x10001000) UICR Structure */ typedef struct { /*!< (@ 0x10001000) UICR Structure */
__IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ __IM uint32_t RESERVED[5];
__IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware
__IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ design */
__IM uint32_t RESERVED; __IM uint32_t RESERVED1[2];
__IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware
__IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic design */
firmware design */ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */
__IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic __IM uint32_t RESERVED2[64];
hardware design */ __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET
__IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ function (see POWER chapter for details) */
__IM uint32_t RESERVED1[64];
__IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET
function */
__IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */
__IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality:
NFC antenna or GPIO */ NFC antenna or GPIO */
__IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */
__IM uint32_t RESERVED2[60]; __IM uint32_t RESERVED3[60];
__IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The
voltage in high voltage mode */ maximum output voltage from this stage is
given as VDDH - VREG0DROP. */
} NRF_UICR_Type; /*!< Size = 776 (0x308) */ } NRF_UICR_Type; /*!< Size = 776 (0x308) */
@ -1015,8 +1011,8 @@ typedef struct { /*!< (@ 0x40000000) CLOCK Struct
typedef struct { /*!< (@ 0x40000000) POWER Structure */ typedef struct { /*!< (@ 0x40000000) POWER Structure */
__IM uint32_t RESERVED[30]; __IM uint32_t RESERVED[30];
__OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */
__OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */
__IM uint32_t RESERVED1[34]; __IM uint32_t RESERVED1[34];
__IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */
__IM uint32_t RESERVED2[2]; __IM uint32_t RESERVED2[2];
@ -1042,9 +1038,9 @@ typedef struct { /*!< (@ 0x40000000) POWER Struct
__IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */
__IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */
__IM uint32_t RESERVED10[21]; __IM uint32_t RESERVED10[21];
__IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage. */ __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */
__IM uint32_t RESERVED11; __IM uint32_t RESERVED11;
__IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage. */ __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage */
__IM uint32_t RESERVED12[47]; __IM uint32_t RESERVED12[47];
__IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */
__IM uint32_t RESERVED13[175]; __IM uint32_t RESERVED13[175];
@ -1053,6 +1049,36 @@ typedef struct { /*!< (@ 0x40000000) POWER Struct
/* =========================================================================================================================== */
/* ================ P0 ================ */
/* =========================================================================================================================== */
/**
* @brief GPIO Port 1 (P0)
*/
typedef struct { /*!< (@ 0x50000000) P0 Structure */
__IM uint32_t RESERVED[321];
__IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
__IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
__IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
__IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
__IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
__IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
__IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
__IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
have met the criteria set in the PIN_CNF[n].SENSE
registers */
__IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
and LDETECT mode */
__IM uint32_t RESERVED1[118];
__IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO
pins */
} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ RADIO ================ */ /* ================ RADIO ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
@ -1112,10 +1138,10 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
__IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */
__IM uint32_t RESERVED3[3]; __IM uint32_t RESERVED3[3];
__IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and
BleIeee802154_250Kbit modes when last bit Ieee802154_250Kbit modes when last bit is
is sent on air. */ sent on air. */
__IM uint32_t RESERVED4[36]; __IM uint32_t RESERVED4[36];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED5[64]; __IM uint32_t RESERVED5[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -1151,9 +1177,9 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
__IM uint32_t RESERVED11[2]; __IM uint32_t RESERVED11[2];
__IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */
__IM uint32_t RESERVED12[39]; __IM uint32_t RESERVED12[39];
__IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment
segment n */ n */
__IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix
n */ n */
__IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */
__IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */
@ -1198,7 +1224,7 @@ typedef struct { /*!< (@ 0x40002000) UART0 Struct
__IM uint32_t RESERVED4[7]; __IM uint32_t RESERVED4[7];
__IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
__IM uint32_t RESERVED5[46]; __IM uint32_t RESERVED5[46];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED6[64]; __IM uint32_t RESERVED6[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -1254,7 +1280,7 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc
__IM uint32_t RESERVED6; __IM uint32_t RESERVED6;
__IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */
__IM uint32_t RESERVED7[41]; __IM uint32_t RESERVED7[41];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED8[63]; __IM uint32_t RESERVED8[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -1337,7 +1363,7 @@ typedef struct { /*!< (@ 0x40003000) SPIM0 Struct
__IM uint32_t RESERVED6[10]; __IM uint32_t RESERVED6[10];
__IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */
__IM uint32_t RESERVED7[44]; __IM uint32_t RESERVED7[44];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED8[64]; __IM uint32_t RESERVED8[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -1391,7 +1417,7 @@ typedef struct { /*!< (@ 0x40003000) SPIS0 Struct
__IM uint32_t RESERVED3[5]; __IM uint32_t RESERVED3[5];
__IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */
__IM uint32_t RESERVED4[53]; __IM uint32_t RESERVED4[53];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED5[64]; __IM uint32_t RESERVED5[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -1405,14 +1431,12 @@ typedef struct { /*!< (@ 0x40003000) SPIS0 Struct
__IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
__IM uint32_t RESERVED10[7]; __IM uint32_t RESERVED10[7];
__IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */
__IM uint32_t RESERVED11;
__IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */
__IM uint32_t RESERVED12;
__IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
__IM uint32_t RESERVED13; __IM uint32_t RESERVED11;
__IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case
of an ignored transaction. */ of an ignored transaction. */
__IM uint32_t RESERVED14[24]; __IM uint32_t RESERVED12[24];
__IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */
} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */
@ -1449,7 +1473,7 @@ typedef struct { /*!< (@ 0x40003000) TWI0 Structu
__IM uint32_t RESERVED7[3]; __IM uint32_t RESERVED7[3];
__IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */
__IM uint32_t RESERVED8[45]; __IM uint32_t RESERVED8[45];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED9[64]; __IM uint32_t RESERVED9[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -1505,7 +1529,7 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct
__IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last
byte */ byte */
__IM uint32_t RESERVED7[39]; __IM uint32_t RESERVED7[39];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED8[63]; __IM uint32_t RESERVED8[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -1557,7 +1581,7 @@ typedef struct { /*!< (@ 0x40003000) TWIS0 Struct
__IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */
__IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */
__IM uint32_t RESERVED7[37]; __IM uint32_t RESERVED7[37];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED8[63]; __IM uint32_t RESERVED8[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -1572,15 +1596,13 @@ typedef struct { /*!< (@ 0x40003000) TWIS0 Struct
__IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
__IM uint32_t RESERVED12[9]; __IM uint32_t RESERVED12[9];
__IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
__IM uint32_t RESERVED13;
__IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
__IM uint32_t RESERVED14[14]; __IM uint32_t RESERVED13[13];
__IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */
n */ __IM uint32_t RESERVED14;
__IM uint32_t RESERVED15;
__IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match
mechanism */ mechanism */
__IM uint32_t RESERVED16[10]; __IM uint32_t RESERVED15[10];
__IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case
of an over-read of the transmit buffer. */ of an over-read of the transmit buffer. */
} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */
@ -1640,7 +1662,7 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu
__IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */
__IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */
__IM uint32_t RESERVED6[43]; __IM uint32_t RESERVED6[43];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED7[63]; __IM uint32_t RESERVED7[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -1687,19 +1709,19 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu
*/ */
typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */
__OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin
pin specified in CONFIG[n].PSEL. Action specified in CONFIG[n].PSEL. Action on pin
on pin is configured in CONFIG[n].POLARITY. */ is configured in CONFIG[n].POLARITY. */
__IM uint32_t RESERVED[4]; __IM uint32_t RESERVED[4];
__OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin
pin specified in CONFIG[n].PSEL. Action specified in CONFIG[n].PSEL. Action on pin
on pin is to set it high. */ is to set it high. */
__IM uint32_t RESERVED1[4]; __IM uint32_t RESERVED1[4];
__OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin
pin specified in CONFIG[n].PSEL. Action specified in CONFIG[n].PSEL. Action on pin
on pin is to set it low. */ is to set it low. */
__IM uint32_t RESERVED2[32]; __IM uint32_t RESERVED2[32];
__IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from
pin specified in CONFIG[n].PSEL */ pin specified in CONFIG[n].PSEL */
__IM uint32_t RESERVED3[23]; __IM uint32_t RESERVED3[23];
__IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins
@ -1708,9 +1730,8 @@ typedef struct { /*!< (@ 0x40006000) GPIOTE Struc
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED5[129]; __IM uint32_t RESERVED5[129];
__IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
OUT[n], SET[n] and CLR[n] tasks and IN[n] SET[n] and CLR[n] tasks and IN[n] event */
event */
} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
@ -1740,7 +1761,7 @@ typedef struct { /*!< (@ 0x40007000) SAADC Struct
__IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */
__IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */
__IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */
__IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */
__IM uint32_t RESERVED1[106]; __IM uint32_t RESERVED1[106];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -1780,13 +1801,13 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc
__OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */
__OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */
__IM uint32_t RESERVED[11]; __IM uint32_t RESERVED[11];
__OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to
to CC[n] register */ CC[n] register */
__IM uint32_t RESERVED1[58]; __IM uint32_t RESERVED1[58];
__IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
match */ match */
__IM uint32_t RESERVED2[42]; __IM uint32_t RESERVED2[42];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED3[64]; __IM uint32_t RESERVED3[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -1796,7 +1817,7 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc
__IM uint32_t RESERVED5; __IM uint32_t RESERVED5;
__IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */
__IM uint32_t RESERVED6[11]; __IM uint32_t RESERVED6[11];
__IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register
n */ n */
} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */
@ -1820,7 +1841,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu
__IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */
__IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */
__IM uint32_t RESERVED1[14]; __IM uint32_t RESERVED1[14];
__IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
match */ match */
__IM uint32_t RESERVED2[109]; __IM uint32_t RESERVED2[109];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -1834,7 +1855,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu
__IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu
t be written when RTC is stopped */ t be written when RTC is stopped */
__IM uint32_t RESERVED5[13]; __IM uint32_t RESERVED5[13];
__IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */
} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */
@ -1898,7 +1919,7 @@ typedef struct { /*!< (@ 0x4000D000) RNG Structur
__IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number
written to the VALUE register */ written to the VALUE register */
__IM uint32_t RESERVED1[63]; __IM uint32_t RESERVED1[63];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[64]; __IM uint32_t RESERVED2[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -1991,7 +2012,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur
__IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */
__IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */
__IM uint32_t RESERVED1[61]; __IM uint32_t RESERVED1[61];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[64]; __IM uint32_t RESERVED2[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -2036,7 +2057,7 @@ typedef struct { /*!< (@ 0x40010000) WDT Structur
__IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */
__IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */
__IM uint32_t RESERVED4[60]; __IM uint32_t RESERVED4[60];
__OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */
} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ } NRF_WDT_Type; /*!< Size = 1568 (0x620) */
@ -2064,7 +2085,7 @@ typedef struct { /*!< (@ 0x40012000) QDEC Structu
__IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */
__IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */
__IM uint32_t RESERVED1[59]; __IM uint32_t RESERVED1[59];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[64]; __IM uint32_t RESERVED2[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -2109,7 +2130,7 @@ typedef struct { /*!< (@ 0x40013000) COMP Structu
__IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */
__IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */
__IM uint32_t RESERVED1[60]; __IM uint32_t RESERVED1[60];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[63]; __IM uint32_t RESERVED2[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -2148,7 +2169,7 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc
__IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */
__IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */
__IM uint32_t RESERVED1[60]; __IM uint32_t RESERVED1[60];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED2[64]; __IM uint32_t RESERVED2[64];
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
@ -2177,10 +2198,10 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc
*/ */
typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ typedef struct { /*!< (@ 0x40014000) EGU0 Structure */
__OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering
the corresponding TRIGGERED[n] event */ the corresponding TRIGGERED[n] event */
__IM uint32_t RESERVED[48]; __IM uint32_t RESERVED[48];
__IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated
by triggering the corresponding TRIGGER[n] by triggering the corresponding TRIGGER[n]
task */ task */
__IM uint32_t RESERVED1[112]; __IM uint32_t RESERVED1[112];
@ -2220,9 +2241,9 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu
__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at
the end of current PWM period, and stops the end of current PWM period, and stops
sequence playback */ sequence playback */
__OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value
value on all enabled channels from sequence on all enabled channels from sequence n,
n, and starts playing that sequence at the and starts playing that sequence at the
rate defined in SEQ[n]REFRESH and/or DECODER.MODE. rate defined in SEQ[n]REFRESH and/or DECODER.MODE.
Causes PWM generation to start if not running. */ Causes PWM generation to start if not running. */
__OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on
@ -2232,16 +2253,16 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu
__IM uint32_t RESERVED1[60]; __IM uint32_t RESERVED1[60];
__IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses
are no longer generated */ are no longer generated */
__IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started
on sequence n */ on sequence n */
__IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every
every sequence n, when last value from RAM sequence n, when last value from RAM has
has been applied to wave counter */ been applied to wave counter */
__IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */
__IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount
of times defined in LOOP.CNT */ of times defined in LOOP.CNT */
__IM uint32_t RESERVED2[56]; __IM uint32_t RESERVED2[56];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED3[63]; __IM uint32_t RESERVED3[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -2366,7 +2387,7 @@ typedef struct { /*!< (@ 0x4001E000) NVMC Structu
*/ */
typedef struct { /*!< (@ 0x4001F000) PPI Structure */ typedef struct { /*!< (@ 0x4001F000) PPI Structure */
__IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */
__IM uint32_t RESERVED[308]; __IM uint32_t RESERVED[308];
__IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */
__IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */
@ -2374,7 +2395,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
__IM uint32_t RESERVED1; __IM uint32_t RESERVED1;
__IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */
__IM uint32_t RESERVED2[148]; __IM uint32_t RESERVED2[148];
__IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */
__IM uint32_t RESERVED3[62]; __IM uint32_t RESERVED3[62];
__IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */
} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ } NRF_PPI_Type; /*!< Size = 2448 (0x990) */
@ -2392,17 +2413,17 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
typedef struct { /*!< (@ 0x40020000) MWU Structure */ typedef struct { /*!< (@ 0x40020000) MWU Structure */
__IM uint32_t RESERVED[64]; __IM uint32_t RESERVED[64];
__IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */
__IM uint32_t RESERVED1[16]; __IM uint32_t RESERVED1[16];
__IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */
__IM uint32_t RESERVED2[100]; __IM uint32_t RESERVED2[100];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED3[5]; __IM uint32_t RESERVED3[5];
__IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */
__IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */
__IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */
__IM uint32_t RESERVED4[53]; __IM uint32_t RESERVED4[53];
__IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */
__IM uint32_t RESERVED5[64]; __IM uint32_t RESERVED5[64];
@ -2430,7 +2451,7 @@ typedef struct { /*!< (@ 0x40025000) I2S Structur
__OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK
generator when this is enabled. */ generator when this is enabled. */
__OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator.
Triggering this task will cause the {event:STOPPED} Triggering this task will cause the STOPPED
event to be generated. */ event to be generated. */
__IM uint32_t RESERVED[63]; __IM uint32_t RESERVED[63];
__IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal
@ -2490,14 +2511,14 @@ typedef struct { /*!< (@ 0x40026000) FPU Structur
typedef struct { /*!< (@ 0x40027000) USBD Structure */ typedef struct { /*!< (@ 0x40027000) USBD Structure */
__IM uint32_t RESERVED; __IM uint32_t RESERVED;
__OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection[n]: Captures the EPIN[n].PTR __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR
and EPIN[n].MAXCNT registers values, and and EPIN[n].MAXCNT registers values, and
enables endpoint IN n to respond to traffic enables endpoint IN n to respond to traffic
from host */ from host */
__OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers
values, and enables sending data on ISO values, and enables sending data on ISO
endpoint */ endpoint */
__OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection[n]: Captures the EPOUT[n].PTR __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR
and EPOUT[n].MAXCNT registers values, and and EPOUT[n].MAXCNT registers values, and
enables endpoint n to respond to traffic enables endpoint n to respond to traffic
from host */ from host */
@ -2519,18 +2540,18 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu
or EPOUT[n].PTR and EPOUT[n].MAXCNT registers or EPOUT[n].PTR and EPOUT[n].MAXCNT registers
have been captured on all endpoints reported have been captured on all endpoints reported
in the EPSTATUS register */ in the EPSTATUS register */
__IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection[n]: The whole EPIN[n] __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer
buffer has been consumed. The RAM buffer has been consumed. The buffer can be accessed
can be accessed safely by software. */ safely by software. */
__IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place
on the control endpoint */ on the control endpoint */
__IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The
RAM buffer can be accessed safely by software. */ buffer can be accessed safely by software. */
__IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection[n]: The whole EPOUT[n] __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer
buffer has been consumed. The RAM buffer has been consumed. The buffer can be accessed
can be accessed safely by software. */ safely by software. */
__IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The
RAM buffer can be accessed safely by software. */ buffer can be accessed safely by software. */
__IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition
has been detected on USB lines */ has been detected on USB lines */
__IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific
@ -2541,7 +2562,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu
__IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint,
indicated by the EPDATASTATUS register */ indicated by the EPDATASTATUS register */
__IM uint32_t RESERVED2[39]; __IM uint32_t RESERVED2[39];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED3[63]; __IM uint32_t RESERVED3[63];
__IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
@ -2648,36 +2669,6 @@ typedef struct { /*!< (@ 0x40029000) QSPI Structu
/* =========================================================================================================================== */
/* ================ P0 ================ */
/* =========================================================================================================================== */
/**
* @brief GPIO Port 1 (P0)
*/
typedef struct { /*!< (@ 0x50000000) P0 Structure */
__IM uint32_t RESERVED[321];
__IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
__IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
__IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
__IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
__IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
__IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
__IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
__IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
have met the criteria set in the PIN_CNF[n].SENSE
registers */
__IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
and LDETECT mode */
__IM uint32_t RESERVED1[118];
__IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO
pins */
} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
/* ================ CC_HOST_RGF ================ */ /* ================ CC_HOST_RGF ================ */
/* =========================================================================================================================== */ /* =========================================================================================================================== */
@ -2747,6 +2738,8 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S
#define NRF_UICR_BASE 0x10001000UL #define NRF_UICR_BASE 0x10001000UL
#define NRF_CLOCK_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL
#define NRF_POWER_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL
#define NRF_P0_BASE 0x50000000UL
#define NRF_P1_BASE 0x50000300UL
#define NRF_RADIO_BASE 0x40001000UL #define NRF_RADIO_BASE 0x40001000UL
#define NRF_UART0_BASE 0x40002000UL #define NRF_UART0_BASE 0x40002000UL
#define NRF_UARTE0_BASE 0x40002000UL #define NRF_UARTE0_BASE 0x40002000UL
@ -2810,12 +2803,10 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S
#define NRF_USBD_BASE 0x40027000UL #define NRF_USBD_BASE 0x40027000UL
#define NRF_UARTE1_BASE 0x40028000UL #define NRF_UARTE1_BASE 0x40028000UL
#define NRF_QSPI_BASE 0x40029000UL #define NRF_QSPI_BASE 0x40029000UL
#define NRF_PWM3_BASE 0x4002D000UL
#define NRF_SPIM3_BASE 0x4002F000UL
#define NRF_P0_BASE 0x50000000UL
#define NRF_P1_BASE 0x50000300UL
#define NRF_CC_HOST_RGF_BASE 0x5002A000UL #define NRF_CC_HOST_RGF_BASE 0x5002A000UL
#define NRF_CRYPTOCELL_BASE 0x5002A000UL #define NRF_CRYPTOCELL_BASE 0x5002A000UL
#define NRF_PWM3_BASE 0x4002D000UL
#define NRF_SPIM3_BASE 0x4002F000UL
/** @} */ /* End of group Device_Peripheral_peripheralAddr */ /** @} */ /* End of group Device_Peripheral_peripheralAddr */
@ -2833,6 +2824,8 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S
#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE)
#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE)
#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE)
#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE)
#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE)
#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE)
#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE)
@ -2896,12 +2889,10 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S
#define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE)
#define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE)
#define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) #define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE)
#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE)
#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE)
#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE)
#define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) #define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE)
#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE)
#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE)
#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE)
/** @} */ /* End of group Device_Peripheral_declaration */ /** @} */ /* End of group Device_Peripheral_declaration */
@ -2911,7 +2902,7 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S
#pragma pop #pragma pop
#elif defined (__ICCARM__) #elif defined (__ICCARM__)
/* leave anonymous unions enabled */ /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050) #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop #pragma clang diagnostic pop
#elif defined (__GNUC__) #elif defined (__GNUC__)
/* anonymous unions are enabled by default */ /* anonymous unions are enabled by default */

2780
cpu/nrf52/include/vendor/nrf52840_bitfields.h vendored
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cpu/nrf52/include/vendor/nrf52_bitfields.h vendored
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@ -1,6 +1,6 @@
/* /*
Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met: modification, are permitted provided that the following conditions are met: