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fe310: Adapt peripherals to use the plic driver

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This commit is contained in:
Koen Zandberg 2020-08-28 20:35:37 +02:00
parent 1d999a1335
commit bef82edf43
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GPG Key ID: 0895A893E6D2985B
5 changed files with 21 additions and 38 deletions
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2
cpu/fe310/Makefile.dep
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@ -10,6 +10,8 @@ USEMODULE += sifive_drivers_fe310
USEMODULE += periph USEMODULE += periph
USEMODULE += periph_pm USEMODULE += periph_pm
FEATURES_REQUIRED += periph_plic
ifneq (,$(filter periph_rtc,$(USEMODULE))) ifneq (,$(filter periph_rtc,$(USEMODULE)))
FEATURES_REQUIRED += periph_rtt FEATURES_REQUIRED += periph_rtt
endif endif

36
cpu/fe310/irq_arch.c
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@ -28,6 +28,7 @@
#include "irq_arch.h" #include "irq_arch.h"
#include "panic.h" #include "panic.h"
#include "sched.h" #include "sched.h"
#include "plic.h"
#include "vendor/encoding.h" #include "vendor/encoding.h"
#include "vendor/platform.h" #include "vendor/platform.h"
@ -38,9 +39,6 @@
volatile int fe310_in_isr = 0; volatile int fe310_in_isr = 0;
/* PLIC external ISR function list */
static external_isr_ptr_t _ext_isrs[PLIC_NUM_INTERRUPTS];
/** /**
* @brief ISR trap vector * @brief ISR trap vector
*/ */
@ -60,7 +58,9 @@ void irq_init(void)
write_csr(mie, 0); write_csr(mie, 0);
/* Initial PLIC external interrupt controller */ /* Initial PLIC external interrupt controller */
PLIC_init(PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES); if (IS_ACTIVE(MODULE_PERIPH_PLIC)) {
plic_init();
}
/* Enable SW and external interrupts */ /* Enable SW and external interrupts */
set_csr(mie, MIP_MSIP); set_csr(mie, MIP_MSIP);
@ -70,30 +70,6 @@ void irq_init(void)
set_csr(mstatus, MSTATUS_DEFAULT); set_csr(mstatus, MSTATUS_DEFAULT);
} }
/**
* @brief Set External ISR callback
*/
void set_external_isr_cb(int intNum, external_isr_ptr_t cbFunc)
{
assert((intNum > 0) && (intNum < PLIC_NUM_INTERRUPTS));
_ext_isrs[intNum] = cbFunc;
}
/**
* @brief External interrupt handler
*/
void external_isr(void)
{
uint32_t intNum = (uint32_t)PLIC_claim_interrupt();
if ((intNum > 0) && (intNum < PLIC_NUM_INTERRUPTS) && (_ext_isrs[intNum] != NULL)) {
_ext_isrs[intNum](intNum);
}
PLIC_complete_interrupt(intNum);
}
/** /**
* @brief Global trap and interrupt handler * @brief Global trap and interrupt handler
*/ */
@ -121,7 +97,9 @@ void handle_trap(uint32_t mcause)
#endif #endif
case IRQ_M_EXT: case IRQ_M_EXT:
/* Handle external interrupt */ /* Handle external interrupt */
external_isr(); if (IS_ACTIVE(MODULE_PERIPH_PLIC)) {
plic_isr_handler();
}
break; break;
default: default:

7
cpu/fe310/periph/gpio.c
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@ -25,6 +25,7 @@
#include "periph_cpu.h" #include "periph_cpu.h"
#include "periph_conf.h" #include "periph_conf.h"
#include "periph/gpio.h" #include "periph/gpio.h"
#include "plic.h"
#include "vendor/encoding.h" #include "vendor/encoding.h"
#include "vendor/platform.h" #include "vendor/platform.h"
#include "vendor/plic_driver.h" #include "vendor/plic_driver.h"
@ -144,9 +145,9 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
clear_csr(mie, MIP_MEIP); clear_csr(mie, MIP_MEIP);
/* Configure GPIO ISR with PLIC */ /* Configure GPIO ISR with PLIC */
set_external_isr_cb(INT_GPIO_BASE + pin, gpio_isr); plic_set_isr_cb(INT_GPIO_BASE + pin, gpio_isr);
PLIC_enable_interrupt(INT_GPIO_BASE + pin); plic_enable_interrupt(INT_GPIO_BASE + pin);
PLIC_set_priority(INT_GPIO_BASE + pin, GPIO_INTR_PRIORITY); plic_set_priority(INT_GPIO_BASE + pin, GPIO_INTR_PRIORITY);
/* Configure the active flank(s) */ /* Configure the active flank(s) */
gpio_irq_enable(pin); gpio_irq_enable(pin);

7
cpu/fe310/periph/rtt.c
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@ -29,6 +29,7 @@
#include "periph_cpu.h" #include "periph_cpu.h"
#include "periph_conf.h" #include "periph_conf.h"
#include "periph/rtt.h" #include "periph/rtt.h"
#include "plic.h"
#include "vendor/encoding.h" #include "vendor/encoding.h"
#include "vendor/platform.h" #include "vendor/platform.h"
#include "vendor/plic_driver.h" #include "vendor/plic_driver.h"
@ -76,9 +77,9 @@ void rtt_init(void)
clear_csr(mie, MIP_MEIP); clear_csr(mie, MIP_MEIP);
/* Configure RTC ISR with PLIC */ /* Configure RTC ISR with PLIC */
set_external_isr_cb(INT_RTCCMP, rtt_isr); plic_set_isr_cb(INT_RTCCMP, rtt_isr);
PLIC_enable_interrupt(INT_RTCCMP); plic_enable_interrupt(INT_RTCCMP);
PLIC_set_priority(INT_RTCCMP, RTT_INTR_PRIORITY); plic_set_priority(INT_RTCCMP, RTT_INTR_PRIORITY);
/* Configure RTC scaler, etc... */ /* Configure RTC scaler, etc... */
AON_REG(AON_RTCCFG) = RTT_SCALE; AON_REG(AON_RTCCFG) = RTT_SCALE;

7
cpu/fe310/periph/uart.c
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@ -25,6 +25,7 @@
#include "irq.h" #include "irq.h"
#include "cpu.h" #include "cpu.h"
#include "periph/uart.h" #include "periph/uart.h"
#include "plic.h"
#include "vendor/encoding.h" #include "vendor/encoding.h"
#include "vendor/platform.h" #include "vendor/platform.h"
#include "vendor/plic_driver.h" #include "vendor/plic_driver.h"
@ -111,9 +112,9 @@ int uart_init(uart_t dev, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
clear_csr(mie, MIP_MEIP); clear_csr(mie, MIP_MEIP);
/* Configure UART ISR with PLIC */ /* Configure UART ISR with PLIC */
set_external_isr_cb(uart_config[dev].isr_num, uart_isr); plic_set_isr_cb(uart_config[dev].isr_num, uart_isr);
PLIC_enable_interrupt(uart_config[dev].isr_num); plic_enable_interrupt(uart_config[dev].isr_num);
PLIC_set_priority(uart_config[dev].isr_num, UART_ISR_PRIO); plic_set_priority(uart_config[dev].isr_num, UART_ISR_PRIO);
/* avoid trap by emptying RX FIFO */ /* avoid trap by emptying RX FIFO */
_drain(dev); _drain(dev);