riot-ci/RIOT
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Merge pull request #14891 from aabadie/pr/boards/stm32f0_default_clock

Browse Source 
boards/stm32f0: introduce default shared clock configuration header
This commit is contained in:
Francisco 2020-09-01 13:37:54 +02:00 committed by GitHub
commit c44a43dadd
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 105 additions and 224 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
boards/common/stm32/include/f0/cfg_clock_default.h Normal file
View File

@ -0,0 +1,68 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default clock configuration for STM32F0
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author José Ignacio Alamos <jialamos@uc.cl>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef F0_CFG_CLOCK_DEFAULT_H
#define F0_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK MHZ(48)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(8)
#endif
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#ifndef CLOCK_LSE
#define CLOCK_LSE (0)
#endif
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#ifndef CLOCK_PLL_PREDIV
#define CLOCK_PLL_PREDIV (1)
#endif
#ifndef CLOCK_PLL_MUL
#define CLOCK_PLL_MUL (6)
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F0_CFG_CLOCK_DEFAULT_H */
/** @} */

32
boards/nucleo-f030r8/include/periph_conf.h
View File

@ -21,40 +21,16 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name Timer configuration
* @{

36
boards/nucleo-f031k6/include/periph_conf.h
View File

@ -20,41 +20,21 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* No HSE available on this board */
#define CLOCK_HSE (0U)
/* Adjust PLL factors when PLL is clocked by HSI */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (12)
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (12)
/** @} */
/**
* @name UART configuration
* @{

36
boards/nucleo-f042k6/include/periph_conf.h
View File

@ -19,41 +19,21 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* No HSE available on this board */
#define CLOCK_HSE (0U)
/* Adjust PLL factors when PLL is clocked by HSI */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (12)
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (12)
/** @} */
/**
* @name UART configuration
* @{

32
boards/nucleo-f070rb/include/periph_conf.h
View File

@ -21,41 +21,17 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name Timer configuration
* @{

32
boards/nucleo-f072rb/include/periph_conf.h
View File

@ -20,41 +20,17 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name Timer configuration
* @{

32
boards/nucleo-f091rc/include/periph_conf.h
View File

@ -19,41 +19,17 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* This board provides an LSE */
#define CLOCK_LSE (1)
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name DMA streams configuration
* @{

29
boards/stm32f030f4-demo/include/periph_conf.h
View File

@ -23,39 +23,12 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name Timer configuration
* @{

3
boards/stm32f0discovery/Makefile.include
View File

@ -1,3 +1,6 @@
# we use shared STM32 configuration snippets
INCLUDES += -I$(RIOTBASE)/boards/common/stm32/include
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

29
boards/stm32f0discovery/include/periph_conf.h
View File

@ -20,39 +20,12 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f0/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 48MHz */
#define CLOCK_CORECLOCK (48000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_APB1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (6)
/** @} */
/**
* @name Timer configuration
* @{