cpu/samd21: adapted to centralized cpu conf
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@ -32,10 +32,8 @@ void cpu_init(void)
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PM->APBBMASK.reg |= PM_APBBMASK_PORT;
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PM->APBBMASK.reg |= PM_APBBMASK_PORT;
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/* disable the watchdog timer */
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/* disable the watchdog timer */
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WDT->CTRL.bit.ENABLE = 0;
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WDT->CTRL.bit.ENABLE = 0;
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/* initialize the Cortex-M core */
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/* set pendSV interrupt to lowest possible priority */
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cortexm_init();
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NVIC_SetPriority(PendSV_IRQn, 0xff);
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/* Initialise clock sources and generic clocks */
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/* Initialise clock sources and generic clocks */
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clk_init();
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clk_init();
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}
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}
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@ -25,29 +25,12 @@ extern "C" {
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#endif
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#endif
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/**
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/**
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* @name Kernel configuration
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* @brief ARM Cortex-M specific CPU configuration
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*
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* TODO: measure and adjust for the cortex-m0
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* @{
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* @{
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*/
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*/
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#define THREAD_EXTRA_STACKSIZE_PRINTF (512)
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_IRQ_NUMOF PERIPH_COUNT_IRQn
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#ifndef THREAD_STACKSIZE_DEFAULT
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#define CPU_FLASH_BASE FLASH_ADDR
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#define THREAD_STACKSIZE_DEFAULT (1024)
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#endif
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#define THREAD_STACKSIZE_IDLE (256)
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/** @} */
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/**
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* @name UART0 buffer size definition for compatibility reasons
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*
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* TODO: remove once the remodeling of the uart0 driver is done
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* @{
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*/
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#ifndef UART0_BUFSIZE
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#define UART0_BUFSIZE (128)
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#endif
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/** @} */
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/** @} */
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/**
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/**
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