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cpu/stm32l0: fix clk control register reset

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on stm32l011, RCC_CR_CSSON is not defined
This commit is contained in:
Alexandre Abadie 2020-10-13 08:34:57 +02:00
parent be261f0138
commit e51279b228
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GPG Key ID: 1C919A403CAE1405
1 changed files with 4 additions and 0 deletions
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cpu/stm32/stmclk/stmclk_l0l1.c
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@ -180,7 +180,11 @@ void stmclk_init_sysclk(void)
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Reset MSION, HSEON, CSSON and PLLON bits */
#ifdef RCC_CR_CSSON
RCC->CR &= ~(RCC_CR_MSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
#else
RCC->CR &= ~(RCC_CR_MSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON);
#endif
/* use HSI as system clock while we do any further configuration and
* configure the AHB and APB clock dividers as configured by the board */