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cpu/stm32: use common CPUID implementation

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This commit is contained in:
Hauke Petersen 2016-02-08 21:54:37 +01:00
parent 7c5bab6ac0
commit ea8db10524
26 changed files with 50 additions and 178 deletions
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5
cpu/stm32_common/include/periph_cpu_common.h
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@ -25,6 +25,11 @@
extern "C" {
#endif
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (12U)
/**
* @brief Use the shared SPI functions
* @{

12
cpu/stm32l1/periph/cpuid.c → cpu/stm32_common/periph/cpuid.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2014-2016 Freie Universität Berlin
* Copyright (C) 2015 James Hollister
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -7,24 +8,27 @@
*/
/**
* @addtogroup cpu_stm32l1
* @addtogroup cpu_stm32_common
* @{
*
* @file
* @brief Low-level CPUID driver implementation
* @brief Implementation of the CPUID driver interface
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
* @author James Hollister <jhollisterjr@gmail.com>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include <stdint.h>
#include <string.h>
#include "periph/cpuid.h"
extern volatile uint32_t _cpuid_address[3];
extern uint32_t *_cpuid_address;
void cpuid_get(void *id)
{
memcpy(id, (void *)(&_cpuid_address), CPUID_LEN);
memcpy(id, _cpuid_address, CPUID_LEN);
}

15
cpu/stm32f0/include/periph_cpu.h
View File

@ -19,26 +19,13 @@
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "cpu.h"
#include "periph_cpu_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (12U)
/**
* @brief declare needed generic SPI functions
* @{
*/
#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
/* to be filled */
#ifdef __cplusplus
}

3
cpu/stm32f0/ldscripts/stm32f051r8.ld
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@ -22,6 +22,9 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f0/ldscripts/stm32f091rc.ld
View File

@ -22,6 +22,9 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

30
cpu/stm32f0/periph/cpuid.c
View File

@ -1,30 +0,0 @@
/*
* Copyright (C) 2015 James Hollister
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f0
* @{
*
* @file
* @brief Low-level CPUID driver implementation
*
* @author James Hollister <jhollisterjr@gmail.com>
*
* @}
*/
#include <string.h>
#include "periph/cpuid.h"
#define STM32F0_CPUID_ADDR (0x1ffff7ac)
void cpuid_get(void *id)
{
memcpy(id, (void *)(STM32F0_CPUID_ADDR), CPUID_LEN);
}

6
cpu/stm32f1/include/periph_cpu.h
View File

@ -19,7 +19,6 @@
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "cpu.h"
#include "periph_cpu_common.h"
#ifdef __cplusplus
@ -44,11 +43,6 @@ typedef uint32_t gpio_t;
*/
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (12U)
/**
* @brief Override values for pull register configuration
* @{

3
cpu/stm32f1/ldscripts/stm32f103c8.ld
View File

@ -22,6 +22,9 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f1/ldscripts/stm32f103cb.ld
View File

@ -22,6 +22,9 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08005000, LENGTH = 128K-0x5000
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f1/ldscripts/stm32f103rb.ld
View File

@ -22,6 +22,9 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f1/ldscripts/stm32f103re.ld
View File

@ -22,6 +22,9 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

28
cpu/stm32f1/periph/cpuid.c
View File

@ -1,28 +0,0 @@
/*
* Copyright (C) 2014-2016 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f1
* @{
*
* @file
* @brief Low-level CPUID driver implementation
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*
* @}
*/
#include <string.h>
#include "periph/cpuid.h"
void cpuid_get(void *id)
{
memcpy(id, (void *)(0x1ffff7e8), CPUID_LEN);
}

6
cpu/stm32f3/include/periph_cpu.h
View File

@ -19,7 +19,6 @@
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "cpu.h"
#include "periph_cpu_common.h"
#ifdef __cplusplus
@ -44,11 +43,6 @@ typedef uint32_t gpio_t;
*/
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (12U)
/**
* @brief Available ports on the STM32F3 family
*/

3
cpu/stm32f3/ldscripts/stm32f303re.ld
View File

@ -25,6 +25,9 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 16K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f3/ldscripts/stm32f303vc.ld
View File

@ -23,6 +23,9 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 8K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f3/ldscripts/stm32f334r8.ld
View File

@ -23,6 +23,9 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 4K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

30
cpu/stm32f3/periph/cpuid.c
View File

@ -1,30 +0,0 @@
/*
* Copyright (C) 2015 James Hollister
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f3
* @{
*
* @file
* @brief Low-level CPUID driver implementation
*
* @author James Hollister <jhollisterjr@gmail.com>
*
* @}
*/
#include <string.h>
#include "periph/cpuid.h"
#define STM32F3_CPUID_ADDR (0x1ffff7ac)
void cpuid_get(void *id)
{
memcpy(id, (void *)(STM32F3_CPUID_ADDR), CPUID_LEN);
}

6
cpu/stm32f4/include/periph_cpu.h
View File

@ -19,7 +19,6 @@
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "cpu.h"
#include "periph_cpu_common.h"
#ifdef __cplusplus
@ -44,11 +43,6 @@ typedef uint32_t gpio_t;
*/
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (12U)
/**
* @brief Available ports on the STM32F4 family
*/

3
cpu/stm32f4/ldscripts/stm32f401re.ld
View File

@ -22,6 +22,9 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f407vg.ld
View File

@ -23,6 +23,9 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f415rg.ld
View File

@ -23,6 +23,9 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

30
cpu/stm32f4/periph/cpuid.c
View File

@ -1,30 +0,0 @@
/*
* Copyright (C) 2015 James Hollister
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f4
* @{
*
* @file
* @brief Low-level CPUID driver implementation
*
* @author James Hollister <jhollisterjr@gmail.com>
*
* @}
*/
#include <string.h>
#include "periph/cpuid.h"
#define STM32F4_CPUID_ADDR (0x1fff7a10)
void cpuid_get(void *id)
{
memcpy(id, (void *)(STM32F4_CPUID_ADDR), CPUID_LEN);
}

6
cpu/stm32l1/include/periph_cpu.h
View File

@ -21,7 +21,6 @@
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "cpu.h"
#include "periph_cpu_common.h"
#ifdef __cplusplus
@ -46,11 +45,6 @@ typedef uint32_t gpio_t;
*/
#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (12U)
/**
* @brief Available ports on the STM32L1 family
*/

6
cpu/stm32l1/ldscripts/stm32l151rba.ld
View File

@ -22,12 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (rw) : ORIGIN = 0x20000000, LENGTH = 32K
/* see STM32L1 Reference Manual (31.2 Unique device ID registers (96 bits))
* Base address:
* - 0x1FF80050 for Cat.1 and Cat.2 devices
* - 0x1FF800D0 for Cat.3, Cat.4, Cat.5 and Cat.6 devices
*/
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
}

6
cpu/stm32l1/ldscripts/stm32l151rc.ld
View File

@ -22,12 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
/* see STM32L1 Reference Manual (31.2 Unique device ID registers (96 bits))
* Base address:
* - 0x1FF80050 for Cat.1 and Cat.2 devices
* - 0x1FF800D0 for Cat.3, Cat.4, Cat.5 and Cat.6 devices
*/
cpuid (r) : ORIGIN = 0x1ff800d0, LENGTH = 12
}

6
cpu/stm32l1/ldscripts/stm32l152ret6.ld
View File

@ -22,12 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 80K
/* see STM32L1 Reference Manual (31.2 Unique device ID registers (96 bits))
* Base address:
* - 0x1FF80050 for Cat.1 and Cat.2 devices
* - 0x1FF800D0 for Cat.3, Cat.4, Cat.5 and Cat.6 devices
*/
cpuid (r) : ORIGIN = 0x1ff800d0, LENGTH = 12
}