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cpu/stm32l4+/wb: centralize max core clock define, adapt related boards

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This commit is contained in:
Alexandre Abadie 2020-10-22 08:48:04 +02:00
parent 05f67a0a00
commit ec5b47fc61
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GPG Key ID: 1C919A403CAE1405
5 changed files with 24 additions and 20 deletions
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7
boards/nucleo-l4r5zi/include/periph_conf.h
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@ -19,11 +19,7 @@
#ifndef PERIPH_CONF_H #ifndef PERIPH_CONF_H
#define PERIPH_CONF_H #define PERIPH_CONF_H
#include "periph_cpu.h"
/* Add specific clock configuration (HSE, LSE) for this board here */ /* Add specific clock configuration (HSE, LSE) for this board here */
#define CLOCK_CORECLOCK_MAX MHZ(120)
#ifndef CONFIG_BOARD_HAS_LSE #ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1 #define CONFIG_BOARD_HAS_LSE 1
#endif #endif
@ -32,7 +28,8 @@
#define CONFIG_CLOCK_PLL_N (30) #define CONFIG_CLOCK_PLL_N (30)
#endif #endif
#include "l4/cfg_clock_default.h" #include "periph_cpu.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h" #include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h" #include "cfg_rtt_default.h"

6
boards/nucleo-l552ze-q/include/periph_conf.h
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@ -20,9 +20,7 @@
#define PERIPH_CONF_H #define PERIPH_CONF_H
/* Add specific clock configuration (HSE, LSE) for this board here */ /* Add specific clock configuration (HSE, LSE) for this board here */
#define CLOCK_CORECLOCK_MAX MHZ(110) /* Reach 108MHz by default by setting custom PLL_N factor */
/* Reach 108MHz by by default setting custom PLL_N factor */
#ifndef CONFIG_CLOCK_PLL_N #ifndef CONFIG_CLOCK_PLL_N
#define CONFIG_CLOCK_PLL_N 27 #define CONFIG_CLOCK_PLL_N 27
#endif #endif
@ -33,7 +31,7 @@
#endif #endif
#include "periph_cpu.h" #include "periph_cpu.h"
#include "l4/cfg_clock_default.h" #include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h" #include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h" #include "cfg_rtt_default.h"
#include "cfg_timer_tim5.h" #include "cfg_timer_tim5.h"

8
boards/p-nucleo-wb55/include/periph_conf.h
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@ -20,11 +20,7 @@
#ifndef PERIPH_CONF_H #ifndef PERIPH_CONF_H
#define PERIPH_CONF_H #define PERIPH_CONF_H
#include "periph_cpu.h"
/* Add specific clock configuration (HSE, LSE) for this board here */ /* Add specific clock configuration (HSE, LSE) for this board here */
#define CLOCK_CORECLOCK_MAX MHZ(64)
#ifndef CONFIG_BOARD_HAS_LSE #ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE 1 #define CONFIG_BOARD_HAS_LSE 1
#endif #endif
@ -39,8 +35,8 @@
#define CLOCK_EXTAHB_DIV RCC_EXTCFGR_C2HPRE_3 #define CLOCK_EXTAHB_DIV RCC_EXTCFGR_C2HPRE_3
#define CLOCK_EXTAHB (CLOCK_CORECLOCK / 2) #define CLOCK_EXTAHB (CLOCK_CORECLOCK / 2)
#include "l4/cfg_clock_default.h" #include "periph_cpu.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h" #include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h" #include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h" #include "cfg_timer_tim2.h"

2
cpu/stm32/include/clk/clk_conf.h
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@ -37,7 +37,7 @@
#include "l0l1/cfg_clock_default.h" #include "l0l1/cfg_clock_default.h"
#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \ #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
defined(CPU_FAM_STM32WB) defined(CPU_FAM_STM32WB)
#include "l4/cfg_clock_default.h" #include "l4l5wb/cfg_clock_default.h"
#else #else
#error "No clock configuration available" #error "No clock configuration available"
#endif #endif

21
cpu/stm32/include/clk/l4/cfg_clock_default.h → cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h
View File

@ -18,8 +18,8 @@
* @author Alexandre Abadie <alexandre.abadie@inria.fr> * @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/ */
#ifndef CLK_L4_CFG_CLOCK_DEFAULT_H #ifndef CLK_L4L5WB_CFG_CLOCK_DEFAULT_H
#define CLK_L4_CFG_CLOCK_DEFAULT_H #define CLK_L4L5WB_CFG_CLOCK_DEFAULT_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -167,9 +167,22 @@ extern "C" {
*/ */
#define CLOCK_CORECLOCK \ #define CLOCK_CORECLOCK \
((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
#ifndef CLOCK_CORECLOCK_MAX
/* Set max allowed sysclk */
#if defined(CPU_FAM_STM32WB)
#define CLOCK_CORECLOCK_MAX MHZ(64)
#elif defined(CPU_FAM_STM32L5)
#define CLOCK_CORECLOCK_MAX MHZ(110)
#elif defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
defined(CPU_LINE_STM32L4S9xx)
#define CLOCK_CORECLOCK_MAX MHZ(120)
#else /* all the other L4 */
#define CLOCK_CORECLOCK_MAX MHZ(80) #define CLOCK_CORECLOCK_MAX MHZ(80)
#endif #endif
#if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX #if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
#if CLOCK_CORECLOCK_MAX == MHZ(64) #if CLOCK_CORECLOCK_MAX == MHZ(64)
#error "SYSCLK cannot exceed 64MHz" #error "SYSCLK cannot exceed 64MHz"
@ -200,5 +213,5 @@ extern "C" {
} }
#endif #endif
#endif /* CLK_L4_CFG_CLOCK_DEFAULT_H */ #endif /* CLK_L4L5WB_CFG_CLOCK_DEFAULT_H */
/** @} */ /** @} */