cpu/stm32f4: add stm32f413vg support
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@ -33,7 +33,7 @@
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#include "vendor/stm32f411xe.h"
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#include "vendor/stm32f411xe.h"
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#elif defined(CPU_MODEL_STM32F412ZG)
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#elif defined(CPU_MODEL_STM32F412ZG)
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#include "vendor/stm32f412zx.h"
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#include "vendor/stm32f412zx.h"
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#elif defined(CPU_MODEL_STM32F413ZH)
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#elif defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F413VG)
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#include "vendor/stm32f413xx.h"
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#include "vendor/stm32f413xx.h"
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#elif defined(CPU_MODEL_STM32F415RG)
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#elif defined(CPU_MODEL_STM32F415RG)
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#include "vendor/stm32f415xx.h"
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#include "vendor/stm32f415xx.h"
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@ -52,7 +52,11 @@ extern "C" {
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* @{
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* @{
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*/
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F413VG)
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#define CPU_IRQ_NUMOF (102U)
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#else
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#define CPU_IRQ_NUMOF (82U)
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#define CPU_IRQ_NUMOF (82U)
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#endif
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#define CPU_FLASH_BASE FLASH_BASE
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#define CPU_FLASH_BASE FLASH_BASE
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/** @} */
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/** @} */
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30
cpu/stm32f4/ldscripts/stm32f413vg.ld
Normal file
30
cpu/stm32f4/ldscripts/stm32f413vg.ld
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@ -0,0 +1,30 @@
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/*
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* Copyright (C) 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_stm32f4
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* @{
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*
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* @file
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* @brief Memory definitions for the STM32F413VG
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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*
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* @}
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*/
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MEMORY
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{
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rom (rx) : ORIGIN = 0x08000000, LENGTH = 1M
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
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cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
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}
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_cpuid_address = ORIGIN(cpuid);
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INCLUDE cortexm_base.ld
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@ -21,8 +21,7 @@
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MEMORY
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MEMORY
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{
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{
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rom (rx) : ORIGIN = 0x08000000, LENGTH = 1536K
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rom (rx) : ORIGIN = 0x08000000, LENGTH = 1536K
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
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ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
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cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
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cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
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}
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}
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