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6185 Commits

Author SHA1 Message Date
Marian Buschsieweke
ac394ce826
cpu/mips32r2_common: Don't access sched_active_* 
Replaced accesses to sched_active_* with API calls in C files
 2020-08-17 12:16:07 +02:00
Marian Buschsieweke
346fb432ed
cpu/fe310: Don't access sched_active_* 
Replaced accesses to sched_active_* with API calls in C files
 2020-08-17 12:16:07 +02:00
Marian Buschsieweke
aeedb3ad16
cpu/cortexm_common: Don't access sched_active_* 
Replaced accesses to sched_active_* with API calls in C files
 2020-08-17 11:27:52 +02:00
Marian Buschsieweke
fa12d9ad52
cpu/atmega_common: Don't access sched_active_* 
Replaced accesses to sched_active_* with API calls in C files
 2020-08-17 11:26:19 +02:00
Marian Buschsieweke
da4979963d
cpu/arm7_common: Don't access sched_active_* 
Replaced accesses to sched_active_* with API calls in C files
 2020-08-17 11:22:03 +02:00
Benjamin Valentin
bdc43c245c cpu/native: RTC: implement rtc_set_alarm() 
Use xtimer to simulate an RTC timer.
This allows to simulate software that makes use of `rtc_set_alarm()`
on native.
 2020-08-16 23:28:30 +02:00
Benjamin Valentin
f0e77840dc cpu/nrf52: spi_twi_irq add workaround for nRF52810 vendor file 
Either nRF52810 should define SPIM_COUNT 2 or nRF52805 should
define SPIM_COUNT 1.
But as it nRF52805 defines SPIM_COUNT 2 and nRF52810 defines SPIM_COUNT 1
even though both have a single SPI and a single, separate TWI peripheral.

Re-define SPIM_COUNT to 2 on nRF52810 as this is the easiest solution.
 2020-08-16 23:26:17 +02:00
Benjamin Valentin
5ecf2e8bb1 cpu/nrf52: ensure PWM is present 
Not all members of the family have a PWM peripheral
 2020-08-16 23:26:17 +02:00
Benjamin Valentin
899e97af30 cpu/nrf52: add definitions for remaining family members 2020-08-16 23:26:17 +02:00
hugues
7b3b10303b cpu/stm32/vectors/vectors_f3: a small fix for STM32F334x8 2020-08-14 14:03:10 +02:00
Cenk Gündoğan
f64511ddb5
Merge pull request #14626 from leandrolanzieri/pr/kconfig/test_modules_kconfig 
kconfig: introduce migration test in CI
 2020-08-13 14:11:00 +02:00
Benjamin Valentin
2509c206ee cpu/lm4f120: GPIO: clear stale interrupt 2020-08-13 10:12:21 +02:00
Alexandre Abadie
7e411ec1b0
Merge pull request #14741 from fjmolinas/pr_fe310_configurable_rtt 
cpu/fe310: add unified rtt configuration
 2020-08-12 18:36:15 +02:00
Francisco Molina
442b11d0ee
cpu/fe310: add unified rtt configuration 2020-08-12 14:46:59 +02:00
Leandro Lanzieri
7dc6639f59
cpu/cortexm_common: add default Kconfig configuration 2020-08-12 12:22:43 +02:00
Leandro Lanzieri
f4e651e26d
cpu/sam0_common: Add default Kconfig configuration 
The configuration file is included by samd21 so it is merged when using
Kconfig.
 2020-08-12 12:22:42 +02:00
Leandro Lanzieri
b98527ef53
cpu: Add 'periph' module to Kconfig 
Select it from cortexm_common module as it is always needed.
 2020-08-12 12:22:39 +02:00
Leandro Lanzieri
0ddd2886b7
cpu/sam0_common: add sam0_common_periph module to Kconfig 2020-08-12 12:22:39 +02:00
Leandro Lanzieri
2d53003ee2
cpu/cortexm_common: Model cortexm_common modules 
This models cortexm_common and cortexm_common_periph modules.
 2020-08-12 12:22:39 +02:00
Leandro Lanzieri
4ad2180f81
kconfig: Add default modules' symbols 2020-08-12 12:22:38 +02:00
Francisco Molina
8ed8daa493
cpu/cc2538/timer: fix 32 bit timer reload value 
The interval load value was only set to 0xffff regardless of the counter
mode used which mad the 32bit timer apparently stop after 0xffff (it
would never reach values >0xffff).

When a GPTM is configured to one of the 32-bit modes, TAILR appears as a
32-bit register (the upper 16-bits correspond to the contents of the
GPTM Timer B Interval Load (TBILR) register). In a 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the
state of TBILR.

Thsi commit set the correct value for TAILR depending on the configured
timer mode.
 2020-08-12 11:35:42 +02:00
benpicco
419ee52ddc
Merge pull request #14711 from benpicco/cpu/sam0_common/gpio-intermediate_irq 
cpu/sam0_common: GPIO: ignore stale interrupts
 2020-08-11 16:32:57 +02:00
benpicco
ea42705637
Merge pull request #14564 from benpicco/cpu/stm32-bitarithm_test_and_clear 
cpu/stm32: GPIO: use bitarithm_test_and_clear()
 2020-08-11 14:05:38 +02:00
benpicco
3ef906c841
Merge pull request #14563 from benpicco/cpu/sam0_common-bitarithm_test_and_clear 
cpu/sam0_common: GPIO: use bitarithm_test_and_clear()
 2020-08-11 14:05:06 +02:00
Francisco
16f47fc893
Merge pull request #14502 from benpicco/cpu/sam0_common/flashpage_cleanup 
cpu/sam0_common: flashpage: clean up implementation
 2020-08-10 08:21:49 +02:00
Marian Buschsieweke
7d9aed7f66
Merge pull request #14391 from benpicco/cpu/stm32-timer_periodic 
cpu/stm32: implement periph_timer_periodic
 2020-08-10 07:58:27 +02:00
Benjamin Valentin
a0972c9e0c cpu/stm32: implement periph_timer_periodic 
Seems like the Interrupt flag for a Capture/Compare channel gets set when

- the CC-value is reached
- the timer resets before the CC value is reached.

We only want the first event and ignore the second one. Unfortunately I did
not find a way to disable the second event type, so it is filtered in software.

That is we need to

 - ignore the CC-interrupts when the COUNT register register is reset
 - ignore the CC-interrupts > TOP value/ARR (auto-reload register)
 2020-08-09 22:55:22 +02:00
Benjamin Valentin
91ad431e34 cpu/nrf52: fix nrf52811 vector definition 
SWI2 was missing - compare with vendor/nrf52811.h
 2020-08-09 21:46:06 +02:00
Benjamin Valentin
4980cb7abe cpu/nrf52: fix nrf52832 vector definition 
The CPU has 39 interrupt vectors and the FPU interrupt is the last one.
(Yes this MCU has an FPU).

Compare with vendor/nrf52.h
 2020-08-09 21:46:06 +02:00
Benjamin Valentin
3f8bb169c6 cpu/nrf52: fix nrf52840 vector definition 
The CPU has 48 interrupt vectors and spi3 is the last one.
See vendor/nrf52840.h
 2020-08-09 21:46:06 +02:00
Benjamin Valentin
ec67798cf0 cpu/nrf52: fix spi_twi_irq for nrf52805/10/11 
These smaller parts have SPI1 mapped to TWI0 (if SPI1 exists at all).
 2020-08-09 21:46:06 +02:00
Benjamin Valentin
ca2b7e1952 cpu/nrf5x_common: UART: capture whole nrf52 lineup 2020-08-09 21:46:06 +02:00
Benjamin Valentin
1713dca711 cpu/nrf52: gpio: fix build for nrf52811 
We can use a more general conditional here.
 2020-08-09 21:46:06 +02:00
Benjamin Valentin
2f236cb092 cpu/nrf52: only enable instruction cache if available 
The instruction cache is not available on all nrf52 MCUs.
 2020-08-09 21:46:06 +02:00
Benjamin Valentin
ea2638dcac cpu/nrf52: split up vector definition 
The interrupt vectors vary between each member of the family.
To retain sanity, split the vectors file up for each MCU.
 2020-08-09 21:46:06 +02:00
Benjamin Valentin
307495985a cpu/nrf52: not all parts have a FPU 2020-08-09 21:46:06 +02:00
Benjamin Valentin
7a9e68af96 cpu/nrf52: add vendor files for nrf52805/10/20/33 2020-08-09 21:46:06 +02:00
Marian Buschsieweke
234a720571
Merge pull request #14516 from benpicco/bitband_hw 
cortexm_common: fix check for bitbanding feature
 2020-08-08 14:26:49 +02:00
Benjamin Valentin
0e22910c94 cpu/sam_common: set CPU_HAS_BITBAND 
- https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf
- http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11100-32-bit%20Cortex-M4-Microcontroller-SAM4S_Datasheet.pdf
 2020-08-08 12:44:11 +02:00
Benjamin Valentin
e886dad430 cpu/lpc1768: set CPU_HAS_BITBAND 
> Support for Cortex-M3 bit banding.

https://www.nxp.com/docs/en/data-sheet/LPC1769_68_67_66_65_64_63.pdf
 2020-08-08 12:44:11 +02:00
Benjamin Valentin
225f56b5e6 cpu/lm4f120: set CPU_HAS_BITBAND 
> A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
> The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. A

https://www.mouser.com/datasheet/2/405/lm4f120h5qr-124014.pdf
 2020-08-08 12:44:11 +02:00
Benjamin Valentin
fae0b00918 cpu/cc26x0: set CPU_HAS_BITBAND 
> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.

https://www.ti.com/lit/ug/swcu117i/swcu117i.pdf
 2020-08-08 12:44:11 +02:00
Benjamin Valentin
098b37a7dc cpu/cc26x2_cc13x2: set CPU_HAS_BITBAND 
> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.

https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf
 2020-08-08 12:44:11 +02:00
Benjamin Valentin
b8d49fe627 cpu/cc2538: set CPU_HAS_BITBAND 2020-08-08 12:44:11 +02:00
Benjamin Valentin
848326bed6 cpu/lpc23xx: RTC: cleanup 
- reduce indentation
 - sanitize logic in rtc_set_alarm()
 - ILR register is clear-on-write, writing 0 has no effect
 2020-08-07 19:25:38 +02:00
benpicco
4635be207b
Merge pull request #14726 from benpicco/riot_epoch 
drivers/periph_common: RTC: use RIOT_EPOCH as the RTC reset value
 2020-08-07 19:07:28 +02:00
Leandro Lanzieri
6b52c53db3
Merge pull request #14614 from aabadie/pr/boards/hifive1_clock_kconfig 
boards/hifive1*: add kconfig options to configure the clock
 2020-08-07 17:40:08 +02:00
Benjamin Valentin
97bf000bcd cpu/stm32: use RIOT_EPOCH 2020-08-07 17:39:25 +02:00
Benjamin Valentin
69c436b891 cpu/ezr32wg: set CPU_HAS_BITBAND 2020-08-07 17:38:38 +02:00
benpicco
a455d74621
Merge pull request #14729 from gschorcht/cpu/esp32/vendor_dependeny_boarddir 
cpu/esp32: remove the dependency of vendor code on BOARDDIR
 2020-08-07 17:03:40 +02:00