Alexandre Abadie
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4b316c593a
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cpu/stm32l0l1: configure MCO
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2020-11-05 13:37:34 +01:00 |
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Alexandre Abadie
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e51279b228
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cpu/stm32l0: fix clk control register reset
on stm32l011, RCC_CR_CSSON is not defined
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2020-10-15 16:24:33 +02:00 |
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Alexandre Abadie
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c14d7ec7db
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cpu/stm32l0l1: refactor clock initialization sequence
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2020-09-22 22:30:20 +02:00 |
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Alexandre Abadie
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425a2f69a2
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cpu/stm32l0l1: ensure PLL is enabled when required
PLL is required for the 48MHz output used by HWRNG and also when it's used as system clock
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2020-09-22 22:30:20 +02:00 |
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Alexandre Abadie
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8ac1909ea3
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cpu: boards: stm32l0l1: use IS_ACTIVE where possible in stmclk
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2020-09-22 22:30:19 +02:00 |
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Alexandre Abadie
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23117a844e
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boards: cpu: stm32l0: rework clock configuration
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2020-09-22 22:30:19 +02:00 |
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Alexandre Abadie
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63a79ae6e4
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cpu/stm32: move stmclk in its own module, remove useless ifdefs
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2020-05-22 21:21:08 +02:00 |
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