5003 Commits

Author SHA1 Message Date
Dylan Laduranty
03b6658721
Merge pull request #13313 from benpicco/samd21-asf
cpu/sam0_common: update samd21 vendor files to version 1.3.395
2020-02-11 21:50:56 +01:00
Alexandre Abadie
3ac25c3ac9
Merge pull request #12556 from bergzand/wip/stusbdev
stm32_common: Add USB OTG FS/HS usbdev peripheral driver
2020-02-11 20:39:46 +01:00
benpicco
de89f3a459
Merge pull request #13319 from maribu/avr-reboot
cpu/atmega_common: Fix reboot issues
2020-02-11 17:18:12 +01:00
Koen Zandberg
bd844435af
stm32: Add dw USB OTG FS usbdev driver 2020-02-11 15:50:18 +01:00
benpicco
628aa1197e
Merge pull request #13331 from btcven/2020_02_10-sram-size
cc26x2_cc13x2: use correct RAM value
2020-02-11 15:43:38 +01:00
Koen Zandberg
c30df3cac9
Merge pull request #7572 from kaspar030/zptr
core: add pointer compression header
2020-02-11 15:25:24 +01:00
benpicco
33291ad675
Merge pull request #13306 from fjmolinas/pr_samr21_use_xosc
boards/sam[r/d]21-xpro: prefer XOSC32K for RTC/RTT (GCLK2)
2020-02-11 15:18:36 +01:00
bbf274aecc cpu/kinetis: immediately convert shell expansion of RAM_BASE_ADDR 2020-02-11 13:59:59 +01:00
496ae49692
Merge pull request #13091 from bergzand/pr/mpu/enable_once
cortexm_common/mpu: Only enable during low low level init
2020-02-11 11:11:13 +01:00
Jean Pierre Dudey
de50518146
cc26x2_cc13x2: use correct RAM value
Previous value was 20 K, now it's 80 K. The older family of these MCUs
(cc13x0, cc26x0) had that size, currently for cc13x2 and cc26x2 it's
80 K.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-02-10 18:38:15 -05:00
Benjamin Valentin
9f4920329b cpu/lpc2387: clear BODR if POR is set
From the data sheet:

> **Note:** Only in case when a reset occurs and the POR = 0, the BODR bit
indicates if the V DD(DCDC)(3V3) voltage was below 2.6 V or not.

So the value of BODR is undefined if POR is set.
Clear it to bring it to a defined state.
2020-02-10 23:04:47 +01:00
Benjamin Valentin
76e19602a2 cpu/lpc2387: rename cpu_woke_from_backup()
The function would always return `true` after early boot, so it
is not very useful for applications.

Now it will only (but always) return true when we woke from Deep Sleep
*after* early boot. This makes it behave the same ways as the function
of the same name on SAME54.

Rename the existing function to cpu_backup_ram_is_initialized() to better
match it's semantics.
2020-02-10 23:04:47 +01:00
Benjamin Valentin
64107dd3a9 cpu/lpc2387: rtc: only initialize RTC after cold boot or external reset
On the MCB2388 plugging the power will result in both the POR and EXTR
bit being set.
Not sure if this is a property of the board, but it means RTC is also
reset after programming, so it behaves just like Backup RAM.

If we woke from Deep Sleep the POR bit will be cleared, so the RTC is not
reset.
2020-02-10 23:04:47 +01:00
Benjamin Valentin
80dde82c86 cpu/lpc2387: clear POR bit if we woke from Deep Sleep
RSIR is 0x1 (POR) if we woke from Deep Sleep.
This makes it hard to distinguish between real power-on and waking from
Deep Sleep, which is why the Backup RAM signature was introduced.

However, calling cpu_woke_from_backup() a second time will always return
true, as the signature will have been set up by early boot then.

Thus, clear the POR bit if the signature was already in place.
The result is:

	RSIR == 0 -> woke from sleep
	RSIR == 1 -> cold boot
2020-02-10 23:04:46 +01:00
Benjamin Valentin
6dbbc8f33a cpu/lpc2387: rtc: remove _rtc_set()
Calling localtime() adds considerable overhead.
There are easier ways to set the date to 1970.

For tests/periph_rtc this results in this ROM change:

master:

   text    data     bss     dec     hex
  31328     240   98064  129632   1fa60

with this patch:

   text    data     bss     dec     hex
  20036     140   98168  118344   1ce48
2020-02-10 23:04:46 +01:00
Francisco
e2dc125fb3
Merge pull request #13308 from maribu/atmega_state_cleanup
cpu/atmega_common: Cleanup state flags
2020-02-10 17:37:24 +01:00
Marian Buschsieweke
60ee8cd513
cpu/atmega_common: Fix pm_reboot with LTO
The reboot process for ATmegas is to enable the watchdog timer and loop until
the wdt reboots this MCU. However, this reboot will keep the wdt configuration,
so that the wdt needs to be disabled during boot. This is done in get_mcusr,
but without the attribute "used" it will be optimized out in LTO builds. This
commits adds the attribute "used" to get_mcusr.

Also simplified the backward compatibility with older ATmegas (currently not
supported by RIOT) on outdated versions of avrlibc.
2020-02-10 17:08:09 +01:00
benpicco
b44cf48a87
Merge pull request #13246 from benpicco/lpc23xx-spi
cpu/lpc2387: make SPI configurable
2020-02-10 17:01:41 +01:00
Benjamin Valentin
13e578bc84 cpu/lpc2387: implement periph/adc
lpc23xx has a 10 bit ADC with up to 8 channels.

The ADC should be clocked at 4.5 MHz or less, so it uses
(72MHz CCLK / 8) / 2.
2020-02-10 13:25:26 +01:00
Benjamin Valentin
e03780c8ca cpu/sam0_common: update samd21 vendor files to version 1.3.395
This release adds EXTINT defines compatible with later versions of
the sam0 series of MCUs.
2020-02-08 03:28:14 +01:00
Dylan Laduranty
b5bb846d3a
Merge pull request #13312 from benpicco/cpu/sam0-vendor_cleanup
cpu/sam0_common: use vendor provided MCU header dispatch
2020-02-07 20:33:45 +01:00
Francisco Molina
238d56e474
cpu/samd21/cpu: reset GCLK before configuring them 2020-02-07 16:11:42 +01:00
Francisco Molina
2e542a2488
cpu/samd21: cleanup XOSC32K initialization 2020-02-07 15:54:56 +01:00
Francisco Molina
9ab22b6926
cpu/samd21: add GEN3_ULP32K selector 2020-02-07 15:53:32 +01:00
benpicco
dfcf155aa6
Merge pull request #13311 from benpicco/cpu/samr21-asf
cpu/sam0_common: update samr21 vendor files to version 1.1.72
2020-02-07 13:06:11 +01:00
Benjamin Valentin
b0078b1a98 cpu/sam0_common: update samr21 vendor files to version 1.1.72
This release adds EXTINT defines compatible with later versions of
the sam0 series of MCUs.
2020-02-07 12:14:45 +01:00
benpicco
66c7c63c94
Merge pull request #13061 from gschorcht/cpu/esp32/rtc_xtal_32k
cpu/esp32: allow external 32 kHz crystal for the RTC hardware timer
2020-02-07 10:24:22 +01:00
Gunar Schorcht
4c0cfdcc8e cpu/esp32: allow external 32 kHz crystal for RTC 2020-02-07 00:46:16 +01:00
Benjamin Valentin
bd1953dd80 cpu/sam0_common: use vendor files to dispatch MCU headers
Instead of manually re-creating the files from ASF, just use
the vendor provided dispatch headers and ease the maintainance
burden.
2020-02-06 19:52:05 +01:00
Benjamin Valentin
fd793b8917 cpu/samd51: add common header file from ASF
Somehow I forgot to commit this.
2020-02-06 19:49:50 +01:00
benpicco
24fb7a9aae
Merge pull request #12933 from maribu/atmega_pcint_cleanup
cpu/atmega_common/periph/gpio: Clean up PCINT support
2020-02-06 18:29:15 +01:00
Marian Buschsieweke
1879f58512
cpu/atmega_common: Cleanup state flags
- Use one byte of RAM to track both IRQ and UART TX state
- Fix incorrect use of volatile
2020-02-06 15:41:41 +01:00
0cb13186cc cpu/atmega32u4: remove obsolete -DCOREIF_NG=1 2020-02-05 15:08:13 +01:00
benpicco
9b33e1ca92
Merge pull request #13271 from kfessel/patch-shed
core/sched: sched.h: remove not needed bitarithm include to avoid conflict
2020-02-05 14:44:08 +01:00
Karl Fessel
4445faaa3a core/shed: remove not needed bitarithm include add missing
bitarithm.h is not needed for the interface of shed but may cause conflicts
due to different definitions of SETBIT and CLRBIT

common implementations are: (value, offset) xor (value, mask) bitarithm
implements the later

frac.c and nrf52/usbdev.c use bitarithm.h but where missing the include

sam0/rtt.c defined a bit using mask from bitarithm,
changed that to the soulution used in sam0/rtc.c
2020-02-05 12:45:29 +01:00
Benjamin Valentin
38b6ee56f3 cpu/sam0: use defines for GCLK IDs
Give the clocks explicit names to better identify their meaning.
2020-02-04 21:16:54 +01:00
Benjamin Valentin
df33ffd0d3 cpu/samd21: only configure one 32kHz GCLK
Use the same 32 kHz GCLK to feed the PLL and the RTT, etc.
2020-02-04 21:16:54 +01:00
Benjamin Valentin
1496149bba cpu/sam0: don't hard-code peripheral clocks
Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK
introduce helper functions to return the frequency of the individual
GCLKs and use those for baud-rate calculations.

This requires the GCLK to be part of the peripheral's config struct.
While this is already the case for most peripherals, this also adds
it for those where it wasn't used before.

As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2020-02-04 21:06:21 +01:00
Benjamin Valentin
a51d167a43 cpu/sam0: use GCLK ID instead of bitmask
To simplify board definitions and for unification between samd2x and
newer models, don't use the GCLK bitmask in board definitions.
Instead use the GCLK index and generate the bitmask when needed.
2020-02-04 21:06:21 +01:00
benpicco
4fb2770fe8
Merge pull request #13279 from benpicco/cc430-rtc-cleanup
cpu/cc430: rtc: remove dead code
2020-02-04 16:56:44 +01:00
Benjamin Valentin
5d96bcf0a0 cpu/cc13x2: fix leftover from cc26x2_cc13x2 rename
A files was forgotten to move and one doxygen group was not renamed.
2020-02-04 14:37:43 +01:00
Benjamin Valentin
1155172106 cpu/cc430: rtc: remove dead code
The commented-out block does provide no value and is confusing
when using `grep`.
2020-02-04 13:20:56 +01:00
benpicco
cc90a896c7
Merge pull request #13166 from jeandudey/2020_01_19-cc26x2-cc13x2
cpu/cc13x2: rename cpu to cc26x2_cc13x2.
2020-02-04 11:45:59 +01:00
Gunar Schorcht
668e05ed4f cpu/atmega: fix PWM compilation error with NDEBUG
When NDEBUG macro is defined during compilation, the assert macro produces empty code. The dev parameter is then unused.
2020-02-03 00:14:32 +01:00
benpicco
5d1bf26f0c
Merge pull request #13076 from gschorcht/boards/esp32/ttgo_t_beam_gps
boards/esp32: enable GPS module on ESP32 TTGO T-Beam V1.0
2020-02-01 23:25:55 +01:00
Gunar Schorcht
3208207ec5 cpu/esp32: change order of board and periph init
To be able to access periphals to initialize board specific hardware, the board_init function has to be called after periph_init.
2020-02-01 16:12:05 +01:00
Benjamin Valentin
3f01f4b183 cpu/lpc2387: make periph/spi configurable 2020-01-31 12:01:09 +01:00
benpicco
d48471a120
Merge pull request #12967 from gschorcht/pkg/lwip/fix_esp_wifi
cpu/esp*: remove dependencies on GNRC for ESP network device drivers
2020-01-31 10:38:08 +01:00
benpicco
cdb427b760
Merge pull request #12475 from francois-berder/wifire-gpio-refactor
cpu: mips_pic32_common: Refactor GPIO peripheral
2020-01-31 09:46:57 +01:00
Gunar Schorcht
208174a006 cpu/esp_common/esp_now: consistent netif thread naming 2020-01-31 09:32:23 +01:00