Alexandre Abadie
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d1724d6718
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cpu/stm32l4: correctly handle clock freq > 80MHz
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2020-10-20 11:37:46 +02:00 |
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Alexandre Abadie
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00ea7ffa55
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cpu/stm32l4wb: cleanup clock initialization
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2020-10-20 11:37:46 +02:00 |
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Alexandre Abadie
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d7d5d9d651
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boards/stm32l4: extend clock configuration
- add PLLQ default value
- better tune default PLLM value depending on HSE value
- ensure CLOCK_PLL_SRC is always defined
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2020-10-20 11:37:45 +02:00 |
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Alexandre Abadie
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b11d65ab70
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cpu/stm32l4: enable PLLQ as 48MHz source if possible
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2020-10-20 11:37:45 +02:00 |
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Alexandre Abadie
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e51279b228
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cpu/stm32l0: fix clk control register reset
on stm32l011, RCC_CR_CSSON is not defined
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2020-10-15 16:24:33 +02:00 |
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Alexandre Abadie
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044acf1175
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cpu/stm32: enable power overdrive on f4 and f7
This is only enabled if the HCLK clock is above 168MHz on F4 and 180MHz on f7
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2020-10-14 13:36:20 +02:00 |
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Alexandre Abadie
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0d786e3dbb
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cpu: boards: stm32f2/f4/f7: rework clock configuration and init
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2020-10-06 16:10:05 +02:00 |
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Alexandre Abadie
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da9168c652
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cpu/stm32: rename stmclk_fx to stmclk_f2f4f7
This commit also removes all f0/f1/f3 specific code from this file
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2020-09-24 11:27:24 +02:00 |
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Alexandre Abadie
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042a550f0d
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boards: cpu: stm32f1/f3: rework clock configuration and init
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2020-09-24 11:27:24 +02:00 |
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Alexandre Abadie
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c14d7ec7db
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cpu/stm32l0l1: refactor clock initialization sequence
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2020-09-22 22:30:20 +02:00 |
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Alexandre Abadie
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425a2f69a2
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cpu/stm32l0l1: ensure PLL is enabled when required
PLL is required for the 48MHz output used by HWRNG and also when it's used as system clock
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2020-09-22 22:30:20 +02:00 |
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Alexandre Abadie
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8ac1909ea3
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cpu: boards: stm32l0l1: use IS_ACTIVE where possible in stmclk
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2020-09-22 22:30:19 +02:00 |
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Alexandre Abadie
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23117a844e
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boards: cpu: stm32l0: rework clock configuration
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2020-09-22 22:30:19 +02:00 |
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Alexandre Abadie
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4e235b8e76
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cpu/stm32l4wb: fix APBx bitfields for divider factor 2
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2020-09-09 15:59:38 +02:00 |
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Francisco
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adb0bcab47
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Merge pull request #14866 from aabadie/pr/boards/stm32l4wb_clock_kconfig
boards: cpu: stm32l4/wb: rework clock configuration and initialization
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2020-09-09 09:35:29 +02:00 |
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Alexandre Abadie
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9dd20c0ccb
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cpu: boards: stm32l4/wb: use IS_USED for clock where possible
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2020-09-08 18:42:42 +02:00 |
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Alexandre Abadie
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0745cc4a99
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cpu: boards: smt32l4: rework clock configuration
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2020-09-08 18:42:41 +02:00 |
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Alexandre Abadie
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7c923da0c8
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cpu/stm32: split f0 clock initialization in separate file
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2020-09-08 16:03:44 +02:00 |
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Alexandre Abadie
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a1038aa70e
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cpu: boards: stm32g4: improve clock configuration
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2020-08-25 12:55:16 +02:00 |
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Alexandre Abadie
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84bbee784d
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cpu/stm32: add transition phase when raising +80MHz clock
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2020-08-24 15:42:13 +02:00 |
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Alexandre Abadie
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dada52ecd2
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cpu/stm32: add stm32g0 support
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2020-07-21 12:45:25 +02:00 |
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Alexandre Abadie
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f546c6238b
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cpu/stm32: add support for stm32g4
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2020-06-19 14:18:17 +02:00 |
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Alexandre Abadie
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7bfdd7718f
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cpu/stm32: introduce CPU_FAM_SHORT variable
This variable contains the short cpu family name: f1, f2, etc.
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2020-05-26 12:27:12 +02:00 |
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Alexandre Abadie
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63a79ae6e4
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cpu/stm32: move stmclk in its own module, remove useless ifdefs
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2020-05-22 21:21:08 +02:00 |
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